From nobody Tue Apr 7 12:24:24 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CA78ECAAD2 for ; Mon, 29 Aug 2022 06:23:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229801AbiH2GXF (ORCPT ); Mon, 29 Aug 2022 02:23:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229756AbiH2GXB (ORCPT ); Mon, 29 Aug 2022 02:23:01 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A442B422E9; Sun, 28 Aug 2022 23:23:00 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27T4B6e0011122; Mon, 29 Aug 2022 06:22:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=dx+V1w4lrq5BxOBMqbomNCog0rYvnxOH+lpnHWblaHU=; b=PdyOIZVSgyXFBNM0IIZsfnhMQ+ePgLowzrKKpl8B/4nc85SrEAdieaoOSKt1ItkILg0D KXsfs0wr5yZT5GVK/lDfu2njnIUI5cTE+qUI1hEIZChvnLWmC5PEU87OekapZkeISJ3X VZkyobpP8X3dX3pWN0s3QfszYYBgagqCA1ZrNsBFDqEImYvwwbz+Kq5hyG5vEjtGqPbM TTzL4QguyQQedBC4vT3RW+c5d30LmwdM/xrNGI4SSL50T4XDmLuwt25Qczfl4pCaUlDB hXoZuqEKfbPci4bdusQXQWVD41DUbg94utpFaRXUjQ4bM23opfjycVfRCo85H9KoBUiU dQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j7ceu3g0q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Aug 2022 06:22:57 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27T6MuDA009536 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Aug 2022 06:22:56 GMT Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Sun, 28 Aug 2022 23:22:52 -0700 From: Satya Priya To: Rob Herring , Bjorn Andersson CC: Douglas Anderson , Stephen Boyd , Andy Gross , , , , , , Subject: [PATCH V8 2/5] clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon Date: Mon, 29 Aug 2022 11:52:30 +0530 Message-ID: <1661754153-14813-3-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661754153-14813-1-git-send-email-quic_c_skakit@quicinc.com> References: <1661754153-14813-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aKi-_SHFHHjoTFbgCSCzhDtPJ0H1RBtH X-Proofpoint-ORIG-GUID: aKi-_SHFHHjoTFbgCSCzhDtPJ0H1RBtH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-29_03,2022-08-25_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 mlxlogscore=751 impostorscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208290030 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode" is enabled in the lpass_aon DT node. Signed-off-by: Satya Priya Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 44 ++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/lpasscc-sc7280.c | 44 ------------------------------= ---- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpas= saudiocc-sc7280.c index 6ab6e5a3..6067328 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -12,6 +12,7 @@ #include #include =20 +#include #include =20 #include "clk-alpha-pll.h" @@ -38,6 +39,32 @@ static const struct pll_vco zonda_vco[] =3D { { 595200000UL, 3600000000UL, 0 }, }; =20 +static struct clk_branch lpass_q6ss_ahbm_clk =3D { + .halt_reg =3D 0x901c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x901c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "lpass_q6ss_ahbm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_clk =3D { + .halt_reg =3D 0x9020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "lpass_q6ss_ahbs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + /* 1128.96MHz configuration */ static const struct alpha_pll_config lpass_audio_cc_pll_config =3D { .l =3D 0x3a, @@ -614,6 +641,11 @@ static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = =3D { .flags =3D RETAIN_FF_ENABLE, }; =20 +static struct clk_regmap *lpass_cc_sc7280_clocks[] =3D { + [LPASS_Q6SS_AHBM_CLK] =3D &lpass_q6ss_ahbm_clk.clkr, + [LPASS_Q6SS_AHBS_CLK] =3D &lpass_q6ss_ahbs_clk.clkr, +}; + static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] =3D { [LPASS_AON_CC_AUDIO_HM_H_CLK] =3D &lpass_aon_cc_audio_hm_h_clk.clkr, [LPASS_AON_CC_VA_MEM0_CLK] =3D &lpass_aon_cc_va_mem0_clk.clkr, @@ -659,6 +691,12 @@ static struct regmap_config lpass_audio_cc_sc7280_regm= ap_config =3D { .fast_io =3D true, }; =20 +static const struct qcom_cc_desc lpass_cc_sc7280_desc =3D { + .config =3D &lpass_audio_cc_sc7280_regmap_config, + .clks =3D lpass_cc_sc7280_clocks, + .num_clks =3D ARRAY_SIZE(lpass_cc_sc7280_clocks), +}; + static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc =3D { .config =3D &lpass_audio_cc_sc7280_regmap_config, .clks =3D lpass_audio_cc_sc7280_clocks, @@ -785,6 +823,12 @@ static int lpass_aon_cc_sc7280_probe(struct platform_d= evice *pdev) if (ret) return ret; =20 + if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) { + lpass_audio_cc_sc7280_regmap_config.name =3D "cc"; + desc =3D &lpass_cc_sc7280_desc; + return qcom_cc_probe(pdev, desc); + } + lpass_audio_cc_sc7280_regmap_config.name =3D "lpasscc_aon"; lpass_audio_cc_sc7280_regmap_config.max_register =3D 0xa0008; desc =3D &lpass_aon_cc_sc7280_desc; diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-s= c7280.c index b39ee1c..5c1e17b 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -17,32 +17,6 @@ #include "clk-branch.h" #include "common.h" =20 -static struct clk_branch lpass_q6ss_ahbm_clk =3D { - .halt_reg =3D 0x1c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "lpass_q6ss_ahbm_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch lpass_q6ss_ahbs_clk =3D { - .halt_reg =3D 0x20, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x20, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "lpass_q6ss_ahbs_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk =3D { .halt_reg =3D 0x0, .halt_check =3D BRANCH_HALT, @@ -105,17 +79,6 @@ static struct regmap_config lpass_regmap_config =3D { .fast_io =3D true, }; =20 -static struct clk_regmap *lpass_cc_sc7280_clocks[] =3D { - [LPASS_Q6SS_AHBM_CLK] =3D &lpass_q6ss_ahbm_clk.clkr, - [LPASS_Q6SS_AHBS_CLK] =3D &lpass_q6ss_ahbs_clk.clkr, -}; - -static const struct qcom_cc_desc lpass_cc_sc7280_desc =3D { - .config =3D &lpass_regmap_config, - .clks =3D lpass_cc_sc7280_clocks, - .num_clks =3D ARRAY_SIZE(lpass_cc_sc7280_clocks), -}; - static struct clk_regmap *lpass_cc_top_sc7280_clocks[] =3D { [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =3D &lpass_top_cc_lpi_q6_axim_hs_clk.clkr, @@ -169,13 +132,6 @@ static int lpass_cc_sc7280_probe(struct platform_devic= e *pdev) if (ret) goto destroy_pm_clk; =20 - lpass_regmap_config.name =3D "cc"; - desc =3D &lpass_cc_sc7280_desc; - - ret =3D qcom_cc_probe_by_index(pdev, 2, desc); - if (ret) - goto destroy_pm_clk; - return 0; =20 destroy_pm_clk: --=20 2.7.4