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Subject: [PATCH v4,2/2] drm: mediatek: Adjust the dpi output format to MT8186
Date: Mon, 29 Aug 2022 11:21:48 +0800
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From: Xinlei Lee <xinlei.lee@mediatek.com>

Dpi output needs to adjust the output format to dual edge for MT8186.

Co-developed-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabor=
a.com>
Reviewed-by: N=C3=ADcolas F. R. A. Prado <nfraprado@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_dpi.c      | 32 +++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_dpi_regs.h |  5 ++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  2 ++
 3 files changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/=
mtk_dpi.c
index fb0b79704636..c23ef7deef26 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -14,6 +14,7 @@
 #include <linux/of_graph.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
 #include <linux/types.h>
=20
 #include <video/videomode.h>
@@ -28,6 +29,7 @@
 #include "mtk_disp_drv.h"
 #include "mtk_dpi_regs.h"
 #include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
=20
 enum mtk_dpi_out_bit_num {
 	MTK_DPI_OUT_BIT_NUM_8BITS,
@@ -80,6 +82,7 @@ struct mtk_dpi {
 	struct pinctrl_state *pins_dpi;
 	u32 output_fmt;
 	int refcount;
+	struct device *mmsys_dev;
 };
=20
 static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b)
@@ -133,6 +136,8 @@ struct mtk_dpi_yc_limit {
  * @yuv422_en_bit: Enable bit of yuv422.
  * @csc_enable_bit: Enable bit of CSC.
  * @pixels_per_iter: Quantity of transferred pixels per iteration.
+ * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to=
 be
+ *		       set in MMSYS.
  */
 struct mtk_dpi_conf {
 	unsigned int (*cal_factor)(int clock);
@@ -151,6 +156,7 @@ struct mtk_dpi_conf {
 	u32 yuv422_en_bit;
 	u32 csc_enable_bit;
 	u32 pixels_per_iter;
+	bool edge_cfg_in_mmsys;
 };
=20
 static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas=
k)
@@ -447,6 +453,9 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi)
 		mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING,
 			     dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE ?
 			     EDGE_SEL : 0, EDGE_SEL);
+		if (dpi->conf->edge_cfg_in_mmsys)
+			mtk_mmsys_ddp_dpi_fmt_config(dpi->mmsys_dev, DPI_RGB888_DDR_CON,
+						     DPI_FORMAT_MASK, NULL);
 	} else {
 		mtk_dpi_mask(dpi, DPI_DDR_SETTING, DDR_EN | DDR_4PHASE, 0);
 	}
@@ -776,8 +785,10 @@ static int mtk_dpi_bind(struct device *dev, struct dev=
ice *master, void *data)
 {
 	struct mtk_dpi *dpi =3D dev_get_drvdata(dev);
 	struct drm_device *drm_dev =3D data;
+	struct mtk_drm_private *priv =3D drm_dev->dev_private;
 	int ret;
=20
+	dpi->mmsys_dev =3D priv->mmsys_dev;
 	ret =3D drm_simple_encoder_init(drm_dev, &dpi->encoder,
 				      DRM_MODE_ENCODER_TMDS);
 	if (ret) {
@@ -928,6 +939,24 @@ static const struct mtk_dpi_conf mt8183_conf =3D {
 	.csc_enable_bit =3D CSC_ENABLE,
 };
=20
+static const struct mtk_dpi_conf mt8186_conf =3D {
+	.cal_factor =3D mt8183_calculate_factor,
+	.reg_h_fre_con =3D 0xe0,
+	.max_clock_khz =3D 150000,
+	.output_fmts =3D mt8183_output_fmts,
+	.num_output_fmts =3D ARRAY_SIZE(mt8183_output_fmts),
+	.edge_cfg_in_mmsys =3D true,
+	.pixels_per_iter =3D 1,
+	.is_ck_de_pol =3D true,
+	.swap_input_support =3D true,
+	.support_direct_pin =3D true,
+	.dimension_mask =3D HPW_MASK,
+	.hvsize_mask =3D HSIZE_MASK,
+	.channel_swap_shift =3D CH_SWAP,
+	.yuv422_en_bit =3D YUV422_EN,
+	.csc_enable_bit =3D CSC_ENABLE,
+};
+
 static const struct mtk_dpi_conf mt8192_conf =3D {
 	.cal_factor =3D mt8183_calculate_factor,
 	.reg_h_fre_con =3D 0xe0,
@@ -1078,6 +1107,9 @@ static const struct of_device_id mtk_dpi_of_ids[] =3D=
 {
 	{ .compatible =3D "mediatek,mt8183-dpi",
 	  .data =3D &mt8183_conf,
 	},
+	{ .compatible =3D "mediatek,mt8186-dpi",
+	  .data =3D &mt8186_conf,
+	},
 	{ .compatible =3D "mediatek,mt8192-dpi",
 	  .data =3D &mt8192_conf,
 	},
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/medi=
atek/mtk_dpi_regs.h
index 62bd4931b344..779e868ffb1a 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
+++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h
@@ -235,4 +235,9 @@
 #define MATRIX_SEL_RGB_TO_JPEG		0
 #define MATRIX_SEL_RGB_TO_BT601		2
=20
+/* Values for DPI configuration in MMSYS address space */
+#define DPI_FORMAT_MASK			0x1
+#define DPI_RGB888_DDR_CON		BIT(0)
+#define DPI_RGB565_SDR_CON		BIT(1)
+
 #endif /* __MTK_DPI_REGS_H */
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media=
tek/mtk_drm_drv.c
index 4eba8339188a..e85b9552e45b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -799,6 +799,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] =
=3D {
 	  .data =3D (void *)MTK_DPI },
 	{ .compatible =3D "mediatek,mt8183-dpi",
 	  .data =3D (void *)MTK_DPI },
+	{ .compatible =3D "mediatek,mt8186-dpi",
+	  .data =3D (void *)MTK_DPI },
 	{ .compatible =3D "mediatek,mt8192-dpi",
 	  .data =3D (void *)MTK_DPI },
 	{ .compatible =3D "mediatek,mt8195-dp-intf",
--=20
2.18.0