From nobody Tue Apr 7 13:31:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FC18C0502A for ; Fri, 26 Aug 2022 22:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345362AbiHZWRr (ORCPT ); Fri, 26 Aug 2022 18:17:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345242AbiHZWQp (ORCPT ); Fri, 26 Aug 2022 18:16:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67ABDE42D9; Fri, 26 Aug 2022 15:16:11 -0700 (PDT) Date: Fri, 26 Aug 2022 22:16:06 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1661552168; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uKRo3ZAgcRMCldFfJp83jPgFF+OBPdKttCcHBUatTp8=; b=3+T2a8E9reWGEfcKnCZnyK5djECAn4RrRIxCoPDQwOKLxGfWS7XzVSJ1sgw+y4krp7dqV0 ohdqI/9QBlJR/+guGzLTZHFbQNt8JgprRfnMd4pI3vW3+5d4Pg6Z4ZVne52X6UfrN6hoLZ 7b6qGDvYKTDb9DBVT9ij9npatu9oq6zugCn38muPKMlG8/3Gur6rF/vtWJsDbtwtbYiCbw R+LejyjGDQKoEHMbMQ5z68w4F9hz8FeO6wzDtP9WJ+f+93dERrhp57yUAKWsONLdwJ63zx F0WqXKeuatGKV2Ob/uFZbvwyOSL64NchSVJ0oiVxUfpyGJ1mjT5EjZ05rYoWAA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1661552168; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uKRo3ZAgcRMCldFfJp83jPgFF+OBPdKttCcHBUatTp8=; b=D8C5jMi/Qu/MbT0RHPBWC3pz9YIbvOziXjhMPOC62xxISCsywwzZktutGZKHwz9p5dw1tm LaackuvqUYvaIVAg== From: "tip-bot2 for Sandipan Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] x86/cpufeatures: Add LbrExtV2 feature bit Cc: Sandipan Das , "Peter Zijlstra (Intel)" , Borislav Petkov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3C172d2b0df39306ed77221c45ee1aa62e8ae0548d=2E16602?= =?utf-8?q?11399=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= References: =?utf-8?q?=3C172d2b0df39306ed77221c45ee1aa62e8ae0548d=2E166021?= =?utf-8?q?1399=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= MIME-Version: 1.0 Message-ID: <166155216685.401.14172488353203745036.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 257449c6a50298bd21dcabd644f66a0296b78532 Gitweb: https://git.kernel.org/tip/257449c6a50298bd21dcabd644f66a029= 6b78532 Author: Sandipan Das AuthorDate: Thu, 11 Aug 2022 17:59:52 +05:30 Committer: Peter Zijlstra CommitterDate: Sat, 27 Aug 2022 00:05:42 +02:00 x86/cpufeatures: Add LbrExtV2 feature bit CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some new performance monitoring features for AMD processors. Bit 1 of EAX indicates support for Last Branch Record Extension Version 2 (LbrExtV2) features. If found to be set during PMU initialization, the EBX bits of the same leaf can be used to determine the number of available LBR entries. For better utilization of feature words, LbrExtV2 is added as a scattered feature bit. [peterz: Rename to AMD_LBR_V2] Signed-off-by: Sandipan Das Signed-off-by: Peter Zijlstra (Intel) Acked-by: Borislav Petkov Link: https://lore.kernel.org/r/172d2b0df39306ed77221c45ee1aa62e8ae0548d.16= 60211399.git.sandipan.das@amd.com --- arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 235dc85..52bdd94 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -96,7 +96,7 @@ #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace = */ #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspac= e */ #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ -/* FREE! ( 3*32+17) */ +#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Exten= sion Version 2 */ #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTS= C */ #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechani= sm */ #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index fd44b54..fc01f81 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, + { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } };