From nobody Tue Apr 7 14:54:57 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53732C0502A for ; Fri, 26 Aug 2022 22:16:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231298AbiHZWQO (ORCPT ); Fri, 26 Aug 2022 18:16:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345031AbiHZWP5 (ORCPT ); Fri, 26 Aug 2022 18:15:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83D89754A9; Fri, 26 Aug 2022 15:15:56 -0700 (PDT) Date: Fri, 26 Aug 2022 22:15:52 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1661552154; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r0mbft+punbjKDvxH9hbakvQEosO8YJTEIL95QEd4c0=; b=2pp//UtgI7hqF8S/8Y3wRBv/EjA9CK0h7Ad07+0QlCU2HGpXJeEAnS0xSeLuppzTQ9I6dP hWX265aMWK5Baw5tFrz4zYTPRQAIUOSmmCQtJChX8/tlwggHMUx8up8++YlPIftBieUylc 90BsIaNFHBtCrLFHwsMnePqAbkaEb9EXreUCS6bWmPeqTedIaC1CkS+4YesGepoXtb4e4/ vifpB5Ttc1tWm7g9jBCejHsWwStyUff+Bf2Zdi1u2ccV6vBJU67v/y8fTsLOgYGjJreHQX FSdsVpTbjcQN8TMxewDUQEvXeWjbQzP3FnwdH0aDuZ31SXhg0l4GIgvbd7nWlQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1661552154; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=r0mbft+punbjKDvxH9hbakvQEosO8YJTEIL95QEd4c0=; b=85gVXGgtfSqq8C8c9CYopOM5vLQQVQ9OEyeL37b+2F3fPMm9QQTbk98WB9Ntv4MCZxPVww 57YePd+7KxiZNdBA== From: "tip-bot2 for Sandipan Das" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/amd/lbr: Add LbrExtV2 branch speculation info support Cc: Stephane Eranian , Sandipan Das , "Peter Zijlstra (Intel)" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: =?utf-8?q?=3Cddc02f6320464cad0e3ff5bdb2314531568a91bc=2E16602?= =?utf-8?q?11399=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= References: =?utf-8?q?=3Cddc02f6320464cad0e3ff5bdb2314531568a91bc=2E166021?= =?utf-8?q?1399=2Egit=2Esandipan=2Edas=40amd=2Ecom=3E?= MIME-Version: 1.0 Message-ID: <166155215274.401.5047464816723154912.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 0bc3be5b4bfd5b75086c26d63584a6f7aaea87d5 Gitweb: https://git.kernel.org/tip/0bc3be5b4bfd5b75086c26d63584a6f7a= aea87d5 Author: Sandipan Das AuthorDate: Thu, 11 Aug 2022 18:00:01 +05:30 Committer: Peter Zijlstra CommitterDate: Sat, 27 Aug 2022 00:05:45 +02:00 perf/x86/amd/lbr: Add LbrExtV2 branch speculation info support Provide branch speculation information captured via AMD Last Branch Record Extension Version 2 (LbrExtV2) by setting the speculation info in branch records. The info is based on the "valid" and "spec" bits in the Branch To registers. Suggested-by: Stephane Eranian Signed-off-by: Sandipan Das Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/ddc02f6320464cad0e3ff5bdb2314531568a91bc.16= 60211399.git.sandipan.das@amd.com --- arch/x86/events/amd/lbr.c | 35 ++++++++++++++++++++++++++++++++--- 1 file changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index eb84f19..2e1c157 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -146,12 +146,19 @@ static void amd_pmu_lbr_filter(void) } } =20 +static const int lbr_spec_map[PERF_BR_SPEC_MAX] =3D { + PERF_BR_SPEC_NA, + PERF_BR_SPEC_WRONG_PATH, + PERF_BR_NON_SPEC_CORRECT_PATH, + PERF_BR_SPEC_CORRECT_PATH, +}; + void amd_pmu_lbr_read(void) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct perf_branch_entry *br =3D cpuc->lbr_entries; struct branch_entry entry; - int out =3D 0, i; + int out =3D 0, idx, i; =20 if (!cpuc->lbr_users) return; @@ -160,8 +167,11 @@ void amd_pmu_lbr_read(void) entry.from.full =3D amd_pmu_lbr_get_from(i); entry.to.full =3D amd_pmu_lbr_get_to(i); =20 - /* Check if a branch has been logged */ - if (!entry.to.split.valid) + /* + * Check if a branch has been logged; if valid =3D 0, spec =3D 0 + * then no branch was recorded + */ + if (!entry.to.split.valid && !entry.to.split.spec) continue; =20 perf_clear_branch_entry_bitfields(br + out); @@ -170,6 +180,25 @@ void amd_pmu_lbr_read(void) br[out].to =3D sign_ext_branch_ip(entry.to.split.ip); br[out].mispred =3D entry.from.split.mispredict; br[out].predicted =3D !br[out].mispred; + + /* + * Set branch speculation information using the status of + * the valid and spec bits. + * + * When valid =3D 0, spec =3D 0, no branch was recorded and the + * entry is discarded as seen above. + * + * When valid =3D 0, spec =3D 1, the recorded branch was + * speculative but took the wrong path. + * + * When valid =3D 1, spec =3D 0, the recorded branch was + * non-speculative but took the correct path. + * + * When valid =3D 1, spec =3D 1, the recorded branch was + * speculative and took the correct path + */ + idx =3D (entry.to.split.valid << 1) | entry.to.split.spec; + br[out].spec =3D lbr_spec_map[idx]; out++; }