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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT089.mail.protection.outlook.com (10.13.175.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.7 via Frontend Transport; Mon, 22 Aug 2022 13:42:52 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:42:50 -0500 Subject: [PATCH v3 01/10] x86/resctrl: Fix min_cbm_bits for AMD From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:42:50 -0500 Message-ID: <166117577023.6695.4825793379162387650.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:42:52.4586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cd7788ac-8426-4fe2-ef45-08da84443616 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5482 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org AMD systems support zero CBM (capacity bit mask) for L3 allocation. That is reflected in rdt_init_res_defs_amd() by: r->cache.arch_has_empty_bitmaps =3D true; However given the unified code in cbm_validate(), checking for: val =3D=3D 0 && !arch_has_empty_bitmaps is not enough because of another check in cbm_validate(): if ((zero_bit - first_bit) < r->cache.min_cbm_bits) The default value of r->cache.min_cbm_bits =3D 1. Leading to: $ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=3D0 > schemata -bash: echo: write error: Invalid argument $ cat /sys/fs/resctrl/info/last_cmd_status Need at least 1 bits in the mask Fix the issue by initializing the min_cbm_bits to 0 for AMD. Also remove the default setting of min_cbm_bits and initialize it separately. After the fix $ cd /sys/fs/resctrl $ mkdir foo $ cd foo $ echo L3:0=3D0 > schemata $ cat /sys/fs/resctrl/info/last_cmd_status ok Link: https://lore.kernel.org/lkml/20220517001234.3137157-1-eranian@google.= com/ Fixes: 316e7f901f5a ("x86/resctrl: Add struct rdt_cache::arch_has_{sparse, = empty}_bitmaps") Signed-off-by: Stephane Eranian Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/core.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index bb1c3f5f60c8..a5c51a14fbce 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -66,9 +66,6 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .rid =3D RDT_RESOURCE_L3, .name =3D "L3", .cache_level =3D 3, - .cache =3D { - .min_cbm_bits =3D 1, - }, .domains =3D domain_init(RDT_RESOURCE_L3), .parse_ctrlval =3D parse_cbm, .format_str =3D "%d=3D%0*x", @@ -83,9 +80,6 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .rid =3D RDT_RESOURCE_L2, .name =3D "L2", .cache_level =3D 2, - .cache =3D { - .min_cbm_bits =3D 1, - }, .domains =3D domain_init(RDT_RESOURCE_L2), .parse_ctrlval =3D parse_cbm, .format_str =3D "%d=3D%0*x", @@ -877,6 +871,7 @@ static __init void rdt_init_res_defs_intel(void) r->cache.arch_has_sparse_bitmaps =3D false; r->cache.arch_has_empty_bitmaps =3D false; r->cache.arch_has_per_cpu_cfg =3D false; + r->cache.min_cbm_bits =3D 1; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_THRTL_BASE; hw_res->msr_update =3D mba_wrmsr_intel; @@ -897,6 +892,7 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_sparse_bitmaps =3D true; r->cache.arch_has_empty_bitmaps =3D true; r->cache.arch_has_per_cpu_cfg =3D true; + r->cache.min_cbm_bits =3D 0; } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; From nobody Fri Apr 10 15:36:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27597C28D13 for ; Mon, 22 Aug 2022 13:43:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235282AbiHVNnG (ORCPT ); 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Mon, 22 Aug 2022 08:42:57 -0500 Subject: [PATCH v3 02/10] x86/cpufeatures: Add Slow Memory Bandwidth Allocation feature flag From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:42:56 -0500 Message-ID: <166117577662.6695.15496626554784059239.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 39caa58e-10d4-47c3-ca86-08da84443a1b X-MS-TrafficTypeDiagnostic: DM5PR12MB2552:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UKS+XRRDmk1fccVDhl+nrK3KBJWp5wTDQl7PaE/imGkd9jRYV9nNmS9Gp4GtaRrjsPO0YReS3IPxkTXCtWrrsgBjqQeg/Ns+3G+zr83f0GyykGHVtJLTKJl8iPyTmfT4TuPvd4v/ILmccXcnweQzKKXatER1avEIndzjGdtK9LVSAlAXvf+C3jCPhsoyZD1htvtZ+vR6Jio6Y/z/t96s/ZzNeaouo64bwshdJrQZaaia3dJQZMvi/H3z5Rt6Nai4pLTkbcg7Egt4lEvYUvF7jydQFDxgxiRU2ZZfws25ZuoP6/KEb/eOup+esrcTwxfr+FEEoQ/+4UT3cPpADSfxqiwtsYk3FDom77MP0QTnGSbQHLwC1JN2sfbavyyDFfJpNZ3fj5BgcRfQtTyXc/H+2xYzZe+fjT0zfEpGA5YPMseHsCAkRvQPN14QCfR7XODynjUu4t/SAzYqzmFUpwdDazGY+peO9SwlI4Sws3z3r9stHlINpIJ/9S8szp1lDqrrLscT84/IRBq+d+Y0mWOLryuOj6bVMb+ap0tbmM4gCv2FNdLxYEi/SD56Iq7/CdW6e0kCAZxP3X/UFtGzKnURq9BgwJ4TOboNtT6YiE+nrlEa7ZrbdT5HO4tK3MNTQ4iLCt1+41hP/u+GspTxEaNi7gRaYZzMs0CD67rYcmPiIp4tMajsCoWBSz/+M1dM7HnP2xTZEMJntftGlv7VPNMrQaTK9U9fGOcls8gYbEWGbP1JGqM3+WdAG01JkfDOQiTZlcWGSFugV2GNCGcp2gOTlfUBc8NKZP5y0xQCA43Ikx+hN2IEqJW4UUC9nGFv4JcbsHfAVbM0aOMUK3h2TBA3s1TGZKkGsBF4XJZOXFk8cESMerUWqFYXWZhY5llZO5BOvzkp17EsPygmSrixbeQmkw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(7916004)(346002)(376002)(136003)(396003)(39860400002)(36840700001)(46966006)(40470700004)(356005)(16576012)(316002)(54906003)(81166007)(110136005)(103116003)(36860700001)(86362001)(82740400003)(82310400005)(41300700001)(83380400001)(26005)(33716001)(40480700001)(966005)(9686003)(478600001)(2906002)(70586007)(70206006)(8936002)(44832011)(5660300002)(8676002)(40460700003)(47076005)(426003)(7416002)(4326008)(186003)(16526019)(336012)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:42:59.2014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39caa58e-10d4-47c3-ca86-08da84443a1b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB2552 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds the new AMD feature X86_FEATURE_SMBA. With this feature, the QOS enforcement policies can be applied to external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. This feature is identified by the CPUID Function 8000_0020_EBX_x0. CPUID Fn8000_0020_EBX_x0 AMD Bandwidth Enforcement Feature Identifiers (ECX= =3D0) Bits Field Name Description 2 L3SBE L3 external slow memory bandwidth enforcement Feature description is available in the specification, "AMD64 Technology Pl= atform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Is= sue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 235dc85c91c3..1815435c9c88 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ +#define X86_FEATURE_SMBA (11*32+18) /* SLOW Memory Bandwidth Allocation */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index fd44b54c90d5..885ecf46abb2 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, + { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT020.mail.protection.outlook.com (10.13.174.149) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.15 via Frontend Transport; Mon, 22 Aug 2022 13:43:05 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:43:03 -0500 Subject: [PATCH v3 03/10] x86/resctrl: Add a new resource type RDT_RESOURCE_SMBA From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:43:02 -0500 Message-ID: <166117578296.6695.6947071073613460712.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:43:05.3285 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: add31c9e-cbbc-4ed5-bbd6-08da84444f31 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5459 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds a new resource type RDT_RESOURCE_SMBA to handle the QoS enforcement policies on the external slow memory. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/core.c | 12 ++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + 2 files changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index a5c51a14fbce..6c38427b71a2 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -100,6 +100,18 @@ struct rdt_hw_resource rdt_resources_all[] =3D { .fflags =3D RFTYPE_RES_MB, }, }, + [RDT_RESOURCE_SMBA] =3D + { + .r_resctrl =3D { + .rid =3D RDT_RESOURCE_SMBA, + .name =3D "SB", + .cache_level =3D 3, + .domains =3D domain_init(RDT_RESOURCE_SMBA), + .parse_ctrlval =3D parse_bw, + .format_str =3D "%d=3D%*u", + .fflags =3D RFTYPE_RES_MB, + }, + }, }; =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 1d647188a43b..24a1dfeb6cb2 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -418,6 +418,7 @@ enum resctrl_res_level { RDT_RESOURCE_L3, RDT_RESOURCE_L2, RDT_RESOURCE_MBA, + RDT_RESOURCE_SMBA, =20 /* Must be the last */ RDT_NUM_RESOURCES, From nobody Fri Apr 10 15:36:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45E45C28D13 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT036.mail.protection.outlook.com (10.13.174.124) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.15 via Frontend Transport; Mon, 22 Aug 2022 13:43:37 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:43:34 -0500 Subject: [PATCH v3 04/10] x86/resctrl: Detect and configure Slow Memory Bandwidth allocation From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:43:09 -0500 Message-ID: <166117578936.6695.16882887771401229703.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:43:37.3935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5706aad3-6123-41c5-749f-08da844450df X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT036.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0058 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QoS slow memory configuration details are available via CPUID_Fn80000020_EDX_x02. Detect the available details and initialize the rest to defaults. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/core.c | 50 +++++++++++++++++++++++++= ++++ arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 + arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 9 +++-- 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 6c38427b71a2..36ad97ab7342 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -253,6 +253,37 @@ static bool __rdt_get_mem_config_amd(struct rdt_resour= ce *r) return true; } =20 +static bool __rdt_get_s_mem_config_amd(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + union cpuid_0x10_3_eax eax; + union cpuid_0x10_x_edx edx; + u32 ebx, ecx; + + cpuid_count(0x80000020, 2, &eax.full, &ebx, &ecx, &edx.full); + hw_res->num_closid =3D edx.split.cos_max + 1; + r->default_ctrl =3D MAX_MBA_BW_AMD; + + /* AMD does not use delay */ + r->membw.delay_linear =3D false; + r->membw.arch_needs_linear =3D false; + + /* + * AMD does not use memory delay throttle model to control + * the allocation like Intel does. + */ + r->membw.throttle_mode =3D THREAD_THROTTLE_UNDEFINED; + r->membw.min_bw =3D 0; + r->membw.bw_gran =3D 1; + /* Max value is 2048, Data width should be 4 in decimal */ + r->data_width =3D 4; + + r->alloc_capable =3D true; + r->alloc_enabled =3D true; + + return true; +} + static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); @@ -787,6 +818,19 @@ static __init bool get_mem_config(void) return false; } =20 +static __init bool get_s_mem_config(void) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_SMBA]; + + if (!rdt_cpu_has(X86_FEATURE_SMBA)) + return false; + + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + return __rdt_get_s_mem_config_amd(&hw_res->r_resctrl); + + return false; +} + static __init bool get_rdt_alloc_resources(void) { struct rdt_resource *r; @@ -817,6 +861,9 @@ static __init bool get_rdt_alloc_resources(void) if (get_mem_config()) ret =3D true; =20 + if (get_s_mem_config()) + ret =3D true; + return ret; } =20 @@ -908,6 +955,9 @@ static __init void rdt_init_res_defs_amd(void) } else if (r->rid =3D=3D RDT_RESOURCE_MBA) { hw_res->msr_base =3D MSR_IA32_MBA_BW_BASE; hw_res->msr_update =3D mba_wrmsr_amd; + } else if (r->rid =3D=3D RDT_RESOURCE_SMBA) { + hw_res->msr_base =3D MSR_IA32_SMBA_BW_BASE; + hw_res->msr_update =3D mba_wrmsr_amd; } } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cp= u/resctrl/ctrlmondata.c index 87666275eed9..11ec3577db40 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -203,7 +203,7 @@ static int parse_line(char *line, struct resctrl_schema= *s, unsigned long dom_id; =20 if (rdtgrp->mode =3D=3D RDT_MODE_PSEUDO_LOCKSETUP && - r->rid =3D=3D RDT_RESOURCE_MBA) { + (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA)) { rdt_last_cmd_puts("Cannot pseudo-lock MBA resource\n"); return -EINVAL; } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 24a1dfeb6cb2..c049a274383c 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -14,6 +14,7 @@ #define MSR_IA32_L2_CBM_BASE 0xd10 #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 +#define MSR_IA32_SMBA_BW_BASE 0xc0000280 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f276aff521e8..fc5286067201 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1218,7 +1218,7 @@ static bool rdtgroup_mode_test_exclusive(struct rdtgr= oup *rdtgrp) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || r->rid =3D=3D RDT_RESOURCE_SMBA) continue; has_cache =3D true; list_for_each_entry(d, &r->domains, list) { @@ -1399,7 +1399,8 @@ static int rdtgroup_size_show(struct kernfs_open_file= *of, ctrl =3D resctrl_arch_get_config(r, d, rdtgrp->closid, schema->conf_type); - if (r->rid =3D=3D RDT_RESOURCE_MBA) + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) size =3D ctrl; else size =3D rdtgroup_cbm_to_size(r, d, ctrl); @@ -2807,7 +2808,9 @@ static int rdtgroup_init_alloc(struct rdtgroup *rdtgr= p) =20 list_for_each_entry(s, &resctrl_schema_all, list) { r =3D s->res; - if (r->rid =3D=3D RDT_RESOURCE_MBA) { + if (r->rid =3D=3D RDT_RESOURCE_MBA || + r->rid =3D=3D RDT_RESOURCE_SMBA) { + rdtgroup_init_mba(r); } else { ret =3D rdtgroup_init_cat(s, rdtgrp->closid); From nobody Fri Apr 10 15:36:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D1F2C32774 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT003.mail.protection.outlook.com (10.13.175.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.15 via Frontend Transport; Mon, 22 Aug 2022 13:43:44 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:43:41 -0500 Subject: [PATCH v3 05/10] x86/cpufeatures: Add Bandwidth Monitoring Event Configuration feature flag From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:43:40 -0500 Message-ID: <166117582066.6695.7752000977572509392.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5dbb3eaa-326b-4880-21fb-08da844454d2 X-MS-TrafficTypeDiagnostic: DS7PR12MB6143:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZQaIv1T5sZJipZ6OkybIOSY4anwGRZmC/0oxOP47Yz5WsSnfHJcFkhFSOIKO5ZtFNRtsmrZkFaRxUzKX8ALRjxs201B8Ogk+5VDd7pJUKCJmjq2JTAwRgT35+qIrJdD8JopNuSO0AT4sJIGWox2yKyupEAnmO1Skjra7OoFr9x/FBkz+VsDjNKJ/0oMLv5txw0UMB3DUdDL/RRUbXq9eKjZuT2YEn6BAtdjgQkc01SNQJPz8dzM4XO/KgVDoRBuEITgrBdhl6u3RR5Y2SOUy7ZRqXWJEaCaqywEQHnlXvTVARVbrJ/ztogxTd26Hj6xV2lBW2Ley3aZRmzb9KTFRPNuN3gJdlEFG3tebc4zKouoj7neBpMqbEVpOM+HweUXUGgvcpZ4NvuJJG1f6LjCxaauiwQxvveUQje2IRjbID2RB53kU3opWAYLypqP/Gnllauw5eBhATM5DBTjLwa5C6ASFP21zqA4PwwujvOgh7EzPPgdx2hzfRNGSJ9IdMVCIoNA+5ClVOd5JwAyVfAylmufbAJHcTeN0pgXYZgmPdc/yg1R1fUBVWy6vVblRFWQznySuvbBoJwQ1lnWgMnDhim/lTJapglskyxNfkHj3HpGk4ls/kAyvChg3or04Ar1nHr7s83T9AeNrKiUsETJ4rh9lYNg3MpwgbZ2qq8fTDZnXm653zntnsOkj40n3eZSw5cjBmZb1PLLqjB6RU7A3RjAoEJ9UFacAVlIXYugnXAyBm2xDURpxcJu6QTNos1FtdvcUJ22F3Njm/VWgsP4FrKghVZNjAhhbgQfcEDFD4Grh7A2sWy7egR/t8hE5XuL2u2ymkV7LHButVgfu1bvk7+T0jFnRRlaV0Hr6LjQ+LVVKNjwT167cL/Dw2FahOMaoUfByH4s/stnoN8nKTDVpHg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(7916004)(376002)(136003)(346002)(396003)(39860400002)(46966006)(40470700004)(36840700001)(966005)(478600001)(16526019)(336012)(8936002)(186003)(47076005)(426003)(9686003)(26005)(2906002)(41300700001)(5660300002)(82310400005)(44832011)(83380400001)(40460700003)(7416002)(40480700001)(316002)(16576012)(33716001)(54906003)(110136005)(70586007)(8676002)(4326008)(70206006)(86362001)(103116003)(81166007)(82740400003)(356005)(36860700001)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:43:44.0171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5dbb3eaa-326b-4880-21fb-08da844454d2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6143 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event Configuration (BMEC). Support of this feature is available via CPUID Fn8000_0020_EBX_x0 (ECX=3D0). Bits Field Name Description 3 EVT_CFG Bandwidth Monitoring Event Configuration (BMEC) Currently, the bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of SLOW memory, the two counters are not enough to count all the different types of memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Each BMEC event has a configuration MSR, QOS_EVT_CFG (0x000_0400h + EventID) which contains one field for each Bandwidth Type that can be used to configure the bandwidth event to track any combination of supported bandwidth types. The event will count requests from every Bandwidth Type bit that is set in the corresponding configuration register. Following are the types of events supported: =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D By default, the mbm_total_bytes configuration is set to 0x7F to count all the event types and the mbm_local_bytes configuration is set to 0x15 to count all the local memory events. Feature description is available in the specification, "AMD64 Technology Platform Quality of Service Extensions, Revision: 1.03 Publication # 56375 Revision: 1.03 Issue Date: February 2022". Link: https://www.amd.com/en/support/tech-docs/amd64-technology-platform-qu= ality-service-extensions Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 1815435c9c88..a4ee02a56d54 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -305,6 +305,7 @@ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime = firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit w= hen EIBRS is enabled */ #define X86_FEATURE_SMBA (11*32+18) /* SLOW Memory Bandwidth Allocation */ +#define X86_FEATURE_BMEC (11*32+18) /* AMD Bandwidth Monitoring Event Con= figuration (BMEC) */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 885ecf46abb2..7981df0b910e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, + { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } }; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT017.mail.protection.outlook.com (10.13.175.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.15 via Frontend Transport; Mon, 22 Aug 2022 13:43:49 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:43:47 -0500 Subject: [PATCH v3 06/10] x86/resctrl: Introduce mon_configurable to detect Bandwidth Monitoring Event Configuration From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:43:47 -0500 Message-ID: <166117582698.6695.3458866624522799072.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:43:49.2971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09fcd433-9293-4df8-1b3d-08da84445806 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT017.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1791 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Newer AMD processors support the new feature Bandwidth Monitoring Event Configuration (BMEC). The events mbm_total_bytes and mbm_local_bytes are configurable when this feature is present. Set mon_configurable if the feature is available. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/monitor.c | 14 ++++++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 17 +++++++++++++++++ include/linux/resctrl.h | 1 + 3 files changed, 32 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index eaf25a234ff5..b9de417dac1c 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -682,6 +682,16 @@ static void l3_mon_evt_init(struct rdt_resource *r) list_add_tail(&mbm_local_event.list, &r->evt_list); } =20 + +void __rdt_get_mon_l3_config_amd(struct rdt_resource *r) +{ + /* + * Check if CPU supports the Bandwidth Monitoring Event Configuration + */ + if (boot_cpu_has(X86_FEATURE_BMEC)) + r->mon_configurable =3D true; +} + int rdt_get_mon_l3_config(struct rdt_resource *r) { unsigned int mbm_offset =3D boot_cpu_data.x86_cache_mbm_width_offset; @@ -714,6 +724,10 @@ int rdt_get_mon_l3_config(struct rdt_resource *r) if (ret) return ret; =20 + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) + __rdt_get_mon_l3_config_amd(r); + + l3_mon_evt_init(r); =20 r->mon_capable =3D true; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index fc5286067201..855483b297a8 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -995,6 +995,16 @@ static int rdt_num_rmids_show(struct kernfs_open_file = *of, return 0; } =20 +static int rdt_mon_configurable_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + + seq_printf(seq, "%d\n", r->mon_configurable); + + return 0; +} + static int rdt_mon_features_show(struct kernfs_open_file *of, struct seq_file *seq, void *v) { @@ -1447,6 +1457,13 @@ static struct rftype res_common_files[] =3D { .seq_show =3D rdt_num_rmids_show, .fflags =3D RF_MON_INFO, }, + { + .name =3D "mon_configurable", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdt_mon_configurable_show, + .fflags =3D RF_MON_INFO, + }, { .name =3D "cbm_mask", .mode =3D 0444, diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 21deb5212bbd..4ee2b606ac14 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -154,6 +154,7 @@ struct rdt_resource { bool mon_enabled; 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Mon, 22 Aug 2022 13:44:21 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT084.mail.protection.outlook.com (10.13.174.194) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.7 via Frontend Transport; Mon, 22 Aug 2022 13:44:21 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:43:53 -0500 Subject: [PATCH v3 07/10] x86/resctrl: Add sysfs interface files to read/write event configuration From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:43:53 -0500 Message-ID: <166117583337.6695.3477964609702763678.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:44:21.0259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc54aa5f-ab24-46d0-d739-08da84446ade X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6950 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add two new sysfs files to read/write the event configuration if the feature Bandwidth Monitoring Event Configuration (BMEC) is supported. The file mbm_local_config is for the configuration of the event mbm_local_bytes and the file mbm_total_config is for the configuration of mbm_total_bytes. $ls /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local* /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config $ls /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total* /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_bytes /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 32 ++++++++++++++++++++++++++++= ++++ 3 files changed, 37 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index c049a274383c..fc725f5e9024 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -72,11 +72,13 @@ DECLARE_STATIC_KEY_FALSE(rdt_mon_enable_key); * struct mon_evt - Entry in the event list of a resource * @evtid: event id * @name: name of the event + * @config: current configuration * @list: entry in &rdt_resource->evt_list */ struct mon_evt { u32 evtid; char *name; + char *config; struct list_head list; }; =20 @@ -95,6 +97,7 @@ union mon_data_bits { unsigned int rid : 10; unsigned int evtid : 8; unsigned int domid : 14; + unsigned int mon_config : 32; } u; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index b9de417dac1c..3f900241dbab 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -656,11 +656,13 @@ static struct mon_evt llc_occupancy_event =3D { static struct mon_evt mbm_total_event =3D { .name =3D "mbm_total_bytes", .evtid =3D QOS_L3_MBM_TOTAL_EVENT_ID, + .config =3D "mbm_total_config", }; =20 static struct mon_evt mbm_local_event =3D { .name =3D "mbm_local_bytes", .evtid =3D QOS_L3_MBM_LOCAL_EVENT_ID, + .config =3D "mbm_local_config", }; =20 /* diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 855483b297a8..30d2182d4fda 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -254,6 +254,10 @@ static const struct kernfs_ops kf_mondata_ops =3D { .seq_show =3D rdtgroup_mondata_show, }; =20 +static const struct kernfs_ops kf_mondata_config_ops =3D { + .atomic_write_len =3D PAGE_SIZE, +}; + static bool is_cpu_list(struct kernfs_open_file *of) { struct rftype *rft =3D of->kn->priv; @@ -2534,6 +2538,25 @@ void rmdir_mondata_subdir_allrdtgrp(struct rdt_resou= rce *r, unsigned int dom_id) } } =20 +static int mon_config_addfile(struct kernfs_node *parent_kn, const char *n= ame, + void *priv) +{ + struct kernfs_node *kn; + int ret =3D 0; + + kn =3D __kernfs_create_file(parent_kn, name, 0644, + GLOBAL_ROOT_UID, GLOBAL_ROOT_GID, 0, + &kf_mondata_config_ops, priv, NULL, NULL); + if (IS_ERR(kn)) + return PTR_ERR(kn); + + ret =3D rdtgroup_kn_set_ugid(kn); + if (ret) + kernfs_remove(kn); + + return ret; +} + static int mkdir_mondata_subdir(struct kernfs_node *parent_kn, struct rdt_domain *d, struct rdt_resource *r, struct rdtgroup *prgrp) @@ -2568,6 +2591,15 @@ static int mkdir_mondata_subdir(struct kernfs_node *= parent_kn, if (ret) goto out_destroy; =20 + /* Create the sysfs event configuration files */ + if (r->mon_configurable && + (mevt->evtid =3D=3D QOS_L3_MBM_TOTAL_EVENT_ID || + mevt->evtid =3D=3D QOS_L3_MBM_LOCAL_EVENT_ID)) { + ret =3D mon_config_addfile(kn, mevt->config, priv.priv); + if (ret) + goto out_destroy; + } + if (is_mbm_event(mevt->evtid)) mon_event_read(&rr, r, d, prgrp, mevt->evtid, true); } From nobody Fri Apr 10 15:36:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE4FC28D13 for ; Mon, 22 Aug 2022 13:44:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234823AbiHVNol (ORCPT ); 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Mon, 22 Aug 2022 08:44:23 -0500 Subject: [PATCH v3 08/10] x86/resctrl: Add the sysfs interface to read the event configuration From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:44:22 -0500 Message-ID: <166117586269.6695.16560984025494646306.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3378ef3e-d8ab-442f-6a65-08da84446d3c X-MS-TrafficTypeDiagnostic: MN2PR12MB3870:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 52GvwyFfEvXyz3rOaiiqiY6KHbFLwuQf32ADQf76f19y+B3CLxKFM7GOuI8tSwtK8OjGuIOsO6b2ndrbMwG1gojuY4pEw4OnBvwqfluDs/zka70/B2FeIzVRU2m7XjdDNfr9HdMLLRX2v6OK8dFRm38zLaJBr2Zs0AyYAQRIb07j6nhgGhEm/4GsNoanqK4iVTWGI2LIN9Gqahq9e637/mYNYdzaPlSF+CxRHVZLjbaOVmjuWlxcoHpcSeH0BNhwHn2o3gAHTGWeDBNB5FCJnVqKWb8+SKyCj+mU0uIo29d/DnNqhGWU24FKoF/Sw8jR1OkYIasAf3zbplaL+3621wsmhUnCipbsN+yS7KG3zm2MAitFR2PT+/tg99FwsGW5ew2QvSgyhsQSNO8aom/eppoJgJYCljJ1F7bgL5WvzU1qmlswXeq21uPW6nqSUb6eu177yHxCGwzM3Cdw1cbVSEIsTbvGqp9Lo9woEwqB8f33IlqaquBZDF6tipa2Qh8aIBtPZIsOJyJMrRl5HaGYLIM+4hZZ0cp7MBpgwghFao7qgc2m5myMFyV2kUcCPob3IhPAk4/UIr1Ke7tY82O2lJsv8hcgx+UwGUV3JtFmhNVBgfQ7JIq0zbMoLwA3IIoJjJD5HQbmV0ionLb1pI6hGRp1W/A5weeXX0jq1MUqFBRDj2aquguoaEFFgMHL7Y//d4xngUAgERKM2IvF+AVCNQ4qLCwsVpt27pkqZSbSEJgU5A005k+EZkaScjfnIyWi/AGNTdGxtygipaxvEhvUDYNHxZEkXlPeVGROY/IcH76JlVJbdnUIZ2YRYJvKte3t95UIrjSltTeg2jryeKYfqQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(4636009)(7916004)(39860400002)(346002)(396003)(136003)(376002)(40470700004)(46966006)(36840700001)(5660300002)(40480700001)(478600001)(83380400001)(16576012)(316002)(82310400005)(26005)(9686003)(54906003)(336012)(16526019)(110136005)(103116003)(36860700001)(66574015)(186003)(82740400003)(81166007)(47076005)(426003)(8676002)(4326008)(70586007)(70206006)(7416002)(2906002)(41300700001)(33716001)(44832011)(40460700003)(356005)(86362001)(8936002)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:44:24.9790 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3378ef3e-d8ab-442f-6a65-08da84446d3c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT084.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3870 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current event configuration can be viewed by the user by reading the sysfs configuration file. Following are the types of events supported. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain By default the mbm_total_bytes configuration is set to 0x7f to count all the types of events and mbm_local_bytes configuration is set to 0x15 to count all the local memory events. $cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config 0x7f $cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config 0x15 Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/internal.h | 21 ++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 70 ++++++++++++++++++++++++++++= ++++ 2 files changed, 91 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index fc725f5e9024..457666709386 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -15,6 +15,7 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 +#define MSR_IA32_EVT_CFG_BASE 0xc0000400 =20 #define MSR_IA32_QM_CTR 0x0c8e #define MSR_IA32_QM_EVTSEL 0x0c8d @@ -50,6 +51,26 @@ */ #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE) =20 +/* Reads to Local DRAM Memory */ +#define READS_TO_LOCAL_MEM BIT(0) + +/* Reads to Remote DRAM Memory */ +#define READS_TO_REMOTE_MEM BIT(1) + +/* Non-Temporal Writes to Local Memory */ +#define NON_TEMP_WRITE_TO_LOCAL_MEM BIT(2) + +/* Non-Temporal Writes to Remote Memory */ +#define NON_TEMP_WRITE_TO_REMOTE_MEM BIT(3) + +/* Reads to Local Memory the system identi=EF=AC=81es as "Slow Memory" */ +#define READS_TO_LOCAL_S_MEM BIT(4) + +/* Reads to Remote Memory the system identi=EF=AC=81es as "Slow Memory" */ +#define READS_TO_REMOTE_S_MEM BIT(5) + +/* Dirty Victims to All Types of Memory */ +#define DIRTY_VICTIS_TO_ALL_MEM BIT(6) =20 struct rdt_fs_context { struct kernfs_fs_context kfc; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 30d2182d4fda..e1847d49fa15 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -254,8 +254,78 @@ static const struct kernfs_ops kf_mondata_ops =3D { .seq_show =3D rdtgroup_mondata_show, }; =20 +/* + * This is called via IPI to read the CQM/MBM counters + * in a domain. + */ +void mon_event_config_read(void *info) +{ + union mon_data_bits *md =3D info; + u32 evtid =3D md->u.evtid; + u32 h, msr_index; + + switch (evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + return; /* Not expected to come here */ + } + + rdmsr(MSR_IA32_EVT_CFG_BASE + msr_index, md->u.mon_config, h); +} + +void mondata_config_read(struct rdt_domain *d, union mon_data_bits *md) +{ + smp_call_function_any(&d->cpu_mask, mon_event_config_read, md, 1); +} + +int rdtgroup_mondata_config_show(struct seq_file *m, void *arg) +{ + struct kernfs_open_file *of =3D m->private; + struct rdt_hw_resource *hw_res; + u32 resid, evtid, domid; + struct rdtgroup *rdtgrp; + struct rdt_resource *r; + union mon_data_bits md; + struct rdt_domain *d; + int ret =3D 0; + + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + ret =3D -ENOENT; + goto out; + } + + md.priv =3D of->kn->priv; + resid =3D md.u.rid; + domid =3D md.u.domid; + evtid =3D md.u.evtid; + + hw_res =3D &rdt_resources_all[resid]; + r =3D &hw_res->r_resctrl; + + d =3D rdt_find_domain(r, domid, NULL); + if (IS_ERR_OR_NULL(d)) { + ret =3D -ENOENT; + goto out; + } + + mondata_config_read(d, &md); + + seq_printf(m, "0x%x\n", md.u.mon_config); + +out: + rdtgroup_kn_unlock(of->kn); + return ret; +} + static const struct kernfs_ops kf_mondata_config_ops =3D { .atomic_write_len =3D PAGE_SIZE, + .seq_show =3D rdtgroup_mondata_config_show, }; =20 static bool is_cpu_list(struct kernfs_open_file *of) From nobody Fri Apr 10 15:36:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A29C28D13 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT079.mail.protection.outlook.com (10.13.175.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5546.7 via Frontend Transport; Mon, 22 Aug 2022 13:45:06 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Mon, 22 Aug 2022 08:45:00 -0500 Subject: [PATCH v3 09/10] x86/resctrl: Add sysfs interface to write the event configuration From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:44:29 -0500 Message-ID: <166117586910.6695.3670808098195387542.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:45:06.5208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9e7bade-7cdc-454d-d0a3-08da844485fc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5248 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the sysfs interface to write the event configuration for the MBM configurable events. The event configuration can be changed by writing to the sysfs file for that specific event. Following are the types of events supported. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Description 6 Dirty Victims from the QOS domain to all types of memory 5 Reads to slow memory in the non-local NUMA domain 4 Reads to slow memory in the local NUMA domain 3 Non-temporal writes to non-local NUMA domain 2 Non-temporal writes to local NUMA domain 1 Reads to memory in the non-local NUMA domain 0 Reads to memory in the local NUMA domain By default the mbm_total_bytes configuration is set to 0x7f to count all the types of events and mbm_local_bytes configuration is set to 0x15 to count all the local memory events. For example: To change the mbm_total_bytes to count all the reads, run the command. $echo 0x33 > /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_config To change the mbm_local_bytes to count all the slow memory reads, run the command. $echo 0x30 > /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_config Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 109 ++++++++++++++++++++++++++++= ++++ 1 file changed, 109 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index e1847d49fa15..83c8780726ff 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -323,9 +323,118 @@ int rdtgroup_mondata_config_show(struct seq_file *m, = void *arg) return ret; } =20 +/* + * This is called via IPI to read the CQM/MBM counters + * in a domain. + */ +void mon_event_config_write(void *info) +{ + union mon_data_bits *md =3D info; + u32 evtid =3D md->u.evtid; + u32 msr_index; + + switch (evtid) { + case QOS_L3_MBM_TOTAL_EVENT_ID: + msr_index =3D 0; + break; + case QOS_L3_MBM_LOCAL_EVENT_ID: + msr_index =3D 1; + break; + default: + return; /* Not expected to come here */ + } + + wrmsr(MSR_IA32_EVT_CFG_BASE + msr_index, md->u.mon_config, 0); +} + +ssize_t rdtgroup_mondata_config_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_hw_resource *hw_res; + struct rdtgroup *rdtgrp; + struct rdt_resource *r; + unsigned int mon_config; + cpumask_var_t cpu_mask; + union mon_data_bits md; + struct rdt_domain *d; + u32 resid, domid; + int ret =3D 0, cpu; + + ret =3D kstrtouint(buf, 0, &mon_config); + if (ret) + return ret; + + rdt_last_cmd_clear(); + + /* mon_config cannot be more than the supported set of events */ + if (mon_config > GENMASK(6, 0)) { + rdt_last_cmd_puts("Invalid event configuration\n"); + return -EINVAL; + } + + cpus_read_lock(); + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + return -ENOENT; + goto e_unlock; + } + + if (!zalloc_cpumask_var(&cpu_mask, GFP_KERNEL)) { + ret =3D -ENOMEM; + goto e_unlock; + } + + + md.priv =3D of->kn->priv; + resid =3D md.u.rid; + domid =3D md.u.domid; + + hw_res =3D &rdt_resources_all[resid]; + r =3D &hw_res->r_resctrl; + d =3D rdt_find_domain(r, domid, NULL); + if (IS_ERR_OR_NULL(d)) { + ret =3D -ENOENT; + goto e_cpumask; + } + + md.u.mon_config =3D mon_config & 0xFF; + + /* Pick all the CPUs in the domain instance */ + for_each_cpu(cpu, &d->cpu_mask) + cpumask_set_cpu(cpu, cpu_mask); + + cpu =3D get_cpu(); + /* Update MSR_IA32_EVT_CFG_BASE MSR on this cpu if it's in cpu_mask */ + if (cpumask_test_cpu(cpu, cpu_mask)) + mon_event_config_write(&md); + + /* Update MSR_IA32_EVT_CFG_BASE MSR on all other cpus in cpu_mask */ + smp_call_function_many(cpu_mask, mon_event_config_write, &md, 1); + put_cpu(); + + /* + * When an Event Configuration is changed, the bandwidth counters + * for all RMIDs and Events will be cleared, and the U-bit for every + * RMID will be set on the next read to any BwEvent for every RMID. + * Clear the mbm_local and mbm_total counts for all the RMIDs. + */ + memset(d->mbm_local, 0, sizeof(struct mbm_state) * r->num_rmid); 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Mon, 22 Aug 2022 08:45:06 -0500 Subject: [PATCH v3 10/10] Documentation/x86: Update resctrl_ui.rst for new features From: Babu Moger To: , , , , CC: , , , , , , , , Date: Mon, 22 Aug 2022 08:45:06 -0500 Message-ID: <166117590621.6695.11208770898633353328.stgit@bmoger-ubuntu> In-Reply-To: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> References: <166117559756.6695.16047463526634290701.stgit@bmoger-ubuntu> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: dc47a3d4-3790-429b-45aa-08da8444873c X-MS-TrafficTypeDiagnostic: MW2PR12MB2489:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3nbyLIux2HcrXsTwUt/CYA0ilEa+CA8lc515g0h8E+lUbtE4wjHqZkmRpVlja0iEI814DnezXus4y9khq/jxe7QQZl1lmUrhjQKQYZHoN4o8gSOC4iFYPO1ROIdYWWNnfh3k7uPd2/YC8WT+hDS3/MjTwLDa5EQ2LYhLxv2annfkuGaEns9354KsL+jA7Kq8mvWhT7ScFIROSON0PSRQ0CnFTc759/ZzgD/M4ajwybJVoH3VGqpY0kdWDB0cBhW40alErAPQrHJiSi8y+5+tAIA43fEOwb7uJzgT+PkmyhmhVryp+mJQYFnSPr/k/w/nOJi7tm21CiEVxeUhEj4521W3oyqBqG5ZsnvjtuY0ymLspc64wSjcLx2Ce7GLgna+iMiWiUwmn1PVmJvuB+qkCs5puBYrm4R93WRWCn/SM4Ru1aR6dyYnUBONsw6Ci4zIcj3w9JVPDbagG9SF4A2aYFmJMO419xsmNWuHyStSuRKp3U1rwU0utwvxSPXfYx6lWwhklti9gxRjwSZwD4oyUnuWrOlO4xrOmEToAldUTTroQ1UFYnpU1iVANMH8v5vXBB0Ey+LyczzyL9asmisdFJTfez/I4EtrGir+LNWVw5l2gr7OKdVCPHn+LObK6yeJYDHOE8Ldw8zce8Ssf5qhjJbeBqy9WCWgwDRniQDZcprKrcXNSvRoFXezFpLbK6XrlC94b3vfGhRuhvTGgH+w3ATegFgoQ6/q6wl/LiiFXtEsJIKFPc922+DBqf6X6qlb43fGO2EohUsp2ZLH5o2S3XLEa7Xxw0kjnTRms+g7+8ds9BGljKNVPYWI+5rT3FhYg3aVQc9A0lx6Eioptlbbxg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230016)(7916004)(4636009)(346002)(39860400002)(396003)(376002)(136003)(36840700001)(46966006)(40470700004)(81166007)(26005)(44832011)(5660300002)(7416002)(2906002)(103116003)(15650500001)(8936002)(9686003)(82310400005)(40460700003)(33716001)(36860700001)(16526019)(426003)(336012)(186003)(86362001)(356005)(83380400001)(40480700001)(47076005)(82740400003)(54906003)(110136005)(41300700001)(8676002)(4326008)(478600001)(70586007)(70206006)(16576012)(316002)(71626007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2022 13:45:08.5988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dc47a3d4-3790-429b-45aa-08da8444873c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2489 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the documentation for the new features: 1. Slow Memory Bandwidth allocation. With this feature, the QOS enforcement policies can be applied to the external slow memory connected to the host. QOS enforcement is accomplished by assigning a Class Of Service (COS) to a processor and specifying allocations or limits for that COS for each resource to be allocated. 2. Bandwidth Monitoring Event Configuration (BMEC). The bandwidth monitoring events mbm_total_bytes and mbm_local_bytes are set to count all the total and local reads/writes respectively. With the introduction of slow memory, the two counters are not enough to count all the different types are memory events. With the feature BMEC, the users have the option to configure mbm_total_bytes and mbm_local_bytes to count the specific type of events. Also add configuration instructions with examples. Signed-off-by: Babu Moger Reviewed-by: Ingo Molnar --- Documentation/x86/resctrl.rst | 126 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 126 insertions(+) diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst index 71a531061e4e..871d0f031ab5 100644 --- a/Documentation/x86/resctrl.rst +++ b/Documentation/x86/resctrl.rst @@ -167,6 +167,12 @@ with the following files: bytes) at which a previously used LLC_occupancy counter can be considered for re-use. =20 +"mon_configurable": + Provides the information if the events mbm_total and + mbm_local are configurable. See the configuration + details for "mbm_total_config" and "mbm_local_config" + for more information. + Finally, in the top level of the "info" directory there is a file named "last_cmd_status". This is reset with every "command" issued via the file system (making new directories or writing to any of the @@ -264,6 +270,32 @@ When monitoring is enabled all MON groups will also co= ntain: the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. =20 +"mbm_total_config", "mbm_local_config": + This contains the current event configuration for the events + mbm_total_bytes and mbm_local_bytes, respectively, when the + Bandwidth Monitoring Event Configuration (BMEC) feature is support= ed. + These files are organized by L3 domains under the subdirectories + "mon_L3_00" and "mon_L3_01". When BMEC is supported, the events + mbm_local_bytes and mbm_total_bytes are configurable. + + Following are the types of events supported: + + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + Bits Description + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + 6 Dirty Victims from the QOS domain to all types of memory + 5 Reads to slow memory in the non-local NUMA domain + 4 Reads to slow memory in the local NUMA domain + 3 Non-temporal writes to non-local NUMA domain + 2 Non-temporal writes to local NUMA domain + 1 Reads to memory in the non-local NUMA domain + 0 Reads to memory in the local NUMA domain + =3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + + By default, the mbm_total_bytes configuration is set to 0x7F to co= unt + all the event types and the mbm_local_bytes configuration is set to + 0x15 to count all the local memory events. + Resource allocation rules ------------------------- =20 @@ -464,6 +496,14 @@ Memory bandwidth domain is L3 cache. =20 MB:=3Dbw_MBps0;=3Dbw_MBps1;... =20 +Slow Memory bandwidth Allocation (when supported) +------------------------------------------------- + +Slow Memory b/w domain is L3 cache. +:: + + SB:=3Dbandwidth0;=3Dbandwidth1;... + Reading/writing the schemata file --------------------------------- Reading the schemata file will show the state of all resources @@ -479,6 +519,44 @@ which you wish to change. E.g. L3DATA:0=3Dfffff;1=3Dfffff;2=3D3c0;3=3Dfffff L3CODE:0=3Dfffff;1=3Dfffff;2=3Dfffff;3=3Dfffff =20 +Reading/writing the schemata file (on AMD systems) +-------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 2GB, you +need to specify the value 16 (16 * 1/8 =3D 2). E.g. +:: + + # cat schemata + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "MB:1=3D16" > schemata + # cat schemata + MB:0=3D2048;1=3D 16;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + +Reading/writing the schemata file (on AMD systems) with slow memory +------------------------------------------------------------------- +Reading the schemata file will show the state of all resources +on all domains. When writing the memory bandwidth allocation you +only need to specify those values in an absolute number expressed +in 1/8 GB/s increments. To allocate bandwidth limit of 8GB, you +need to specify the value 64 (64 * 1/8 =3D 8). E.g. +:: + + # cat schemata + SB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + + # echo "SB:1=3D64" > schemata + # cat schemata + SB:0=3D2048;1=3D 64;2=3D2048;3=3D2048 + MB:0=3D2048;1=3D2048;2=3D2048;3=3D2048 + L3:0=3Dffff;1=3Dffff;2=3Dffff;3=3Dffff + Cache Pseudo-Locking =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D CAT enables a user to specify the amount of cache space that an @@ -1210,6 +1288,54 @@ View the llc occupancy snapshot:: # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/llc_occupancy 11234000 =20 +Example 5 (Configure and Monitor specific event types) +------------------------------------------------------ + +A single socket system which has real time tasks running on cores 0-4 +and non real time tasks on other CPUs. We want to monitor the memory +bandwidth allocation for specific events. +:: + + # mount -t resctrl resctrl /sys/fs/resctrl + # cd /sys/fs/resctrl + # mkdir p1 + +Move the CPUs 0-4 over to p1:: + + # echo 0xf > p1/cpus + +View the current mbm_local_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_bytes + 112501 + +Change the mbm_local_bytes to count mon-temporal writes to both local +and non-local NUMA domain. Refer to event supported bitmap under +mbm_local_config:: + + # echo 0xc > /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_config + +View the updated mbm_local_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_local_bytes + 12601 + +Similar experiment on mbm_total_bytes. First view the current mbm_total_by= tes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_bytes + 1532501 + +Change the mbm_total_bytes to count only reads to slow memory on both local +and non-local NUMA domain. Refer to event supported bitmap under +mbm_total_config:: + + # echo 0x30 > /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_config + +View the updated mbm_total_bytes:: + + # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/mbm_total_bytes + 104562 + Intel RDT Errata =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20