From nobody Sun Apr 12 00:06:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1D48C19F2D for ; Thu, 4 Aug 2022 10:29:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239153AbiHDK3K (ORCPT ); Thu, 4 Aug 2022 06:29:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232471AbiHDK3I (ORCPT ); Thu, 4 Aug 2022 06:29:08 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32083422C5; Thu, 4 Aug 2022 03:29:07 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 274A9UUG023791; Thu, 4 Aug 2022 10:29:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id; s=qcppdkim1; bh=EZe8eC3iDD3kk/ONKmOPiIysE9i0w67BBMmkWHWW3H0=; b=FBoIiZmGu46jChSLNNt60yA4a4inoaJYCyOSbJdw4LeZdChhTBfLw2Gh//h0nuhVHUGw 9BmR1qYBSBKQoTyRKUDlbJWLtvO1O72rD2uFhIUl3EZCmXQ8Mbh+9ThrUwOIFWMPOykR akPO7ZzQQ4i1AlsUFd0rx+3OEbpWA96gJWzV5oy+DWq2HYw7NaVrNwQp13l1qVVHmcSM 0WsLpNHCASVvvcm2pKJkXZJ+Jw289QtCUfZOUvBvNLm+pdMQGTBWCv0sFT2fWSv9CUIa BC3sPFy+ya76OqwyT79KWnHbgArzN57UQQK8qAij/WAStAU+rKur3WX7IhQWtFTpYPf3 xQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3hqy7r9cu3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 04 Aug 2022 10:29:03 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 274ASxPf017796; Thu, 4 Aug 2022 10:28:59 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3hmwqkg9n7-1; Thu, 04 Aug 2022 10:28:59 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 274ASwq7017791; Thu, 4 Aug 2022 10:28:58 GMT Received: from kalyant-linux.qualcomm.com (kalyant-linux.qualcomm.com [10.204.66.210]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 274ASwYO017790; Thu, 04 Aug 2022 10:28:58 +0000 Received: by kalyant-linux.qualcomm.com (Postfix, from userid 94428) id D9F5E40F4; Thu, 4 Aug 2022 03:28:57 -0700 (PDT) From: Kalyan Thota To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Kalyan Thota , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_vpolimer@quicinc.com, dmitry.baryshkov@linaro.org, quic_abhinavk@quicinc.com Subject: [v1] drm/msm/disp/dpu1: add support for hierarchical flush for dspp in sc7280 Date: Thu, 4 Aug 2022 03:28:50 -0700 Message-Id: <1659608930-4370-1-git-send-email-quic_kalyant@quicinc.com> X-Mailer: git-send-email 2.7.4 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1ZUH6sWsyGbNWSu42OdW5FXzlwGvlRt5 X-Proofpoint-ORIG-GUID: 1ZUH6sWsyGbNWSu42OdW5FXzlwGvlRt5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-04_03,2022-08-04_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1011 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2208040045 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Flush mechanism for DSPP blocks has changed in sc7280 family, it allows individual sub blocks to be flushed in coordination with master flush control. representation: master_flush && (PCC_flush | IGC_flush .. etc ) This change adds necessary support for the above design. Signed-off-by: Kalyan Thota --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 40 ++++++++++++++++++++++= +++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 3 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 7 +++++ 6 files changed, 59 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 7763558..4eca317 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -703,6 +703,10 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc = *crtc) mixer[i].flush_mask |=3D ctl->ops.get_bitmask_dspp(ctl, mixer[i].hw_dspp->idx); =20 + if(ctl->ops.set_dspp_hierarchical_flush) + ctl->ops.set_dspp_hierarchical_flush(ctl, + mixer[i].hw_dspp->idx, DSPP_SUB_PCC); + /* stage config flush mask */ ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 021eb2f..3b27a87 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -58,7 +58,10 @@ (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) =20 #define CTL_SC7280_MASK \ - (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG= )) + (BIT(DPU_CTL_ACTIVE_CFG) | \ + BIT(DPU_CTL_FETCH_ACTIVE) | \ + BIT(DPU_CTL_VM_CFG) | \ + BIT(DPU_CTL_HIERARCHICAL_FLUSH)) =20 #define MERGE_3D_SM8150_MASK (0) =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index b85b24b..7922f6c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -185,6 +185,7 @@ enum { * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) * @DPU_CTL_VM_CFG: CTL config to support multiple VMs + * @DPU_CTL_HIERARCHICAL_FLUSH: CTL config to support hierarchical flush * @DPU_CTL_MAX */ enum { @@ -192,6 +193,7 @@ enum { DPU_CTL_ACTIVE_CFG, DPU_CTL_FETCH_ACTIVE, DPU_CTL_VM_CFG, + DPU_CTL_HIERARCHICAL_FLUSH, DPU_CTL_MAX }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 3584f5e..b34fc30 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -28,6 +28,8 @@ #define CTL_INTF_FLUSH 0x110 #define CTL_INTF_MASTER 0x134 #define CTL_FETCH_PIPE_ACTIVE 0x0FC +#define CTL_DSPP_0_FLUSH 0x13C + =20 #define CTL_MIXER_BORDER_OUT BIT(24) #define CTL_FLUSH_MASK_CTL BIT(17) @@ -292,6 +294,36 @@ static uint32_t dpu_hw_ctl_get_bitmask_dspp(struct dpu= _hw_ctl *ctx, return flushbits; } =20 +static uint32_t dpu_hw_ctl_get_bitmask_dspp_v1(struct dpu_hw_ctl *ctx, + enum dpu_dspp dspp) +{ + return BIT(29); +} + +static void dpu_hw_ctl_set_dspp_hierarchical_flush(struct dpu_hw_ctl *ctx, + enum dpu_dspp dspp, enum dpu_dspp_sub_blk dspp_sub_blk) +{ + uint32_t flushbits =3D 0, active =3D 0; + + switch (dspp_sub_blk) { + case DSPP_SUB_IGC: + flushbits =3D BIT(2); + break; + case DSPP_SUB_PCC: + flushbits =3D BIT(4); + break; + case DSPP_SUB_GC: + flushbits =3D BIT(5); + break; + default: + return; + } + + active =3D DPU_REG_READ(&ctx->hw, CTL_DSPP_0_FLUSH + ((dspp - 1) * 4)); + + DPU_REG_WRITE(&ctx->hw, CTL_DSPP_0_FLUSH + ((dspp - 1) * 4), active | flu= shbits); +} + static u32 dpu_hw_ctl_poll_reset_status(struct dpu_hw_ctl *ctx, u32 timeou= t_us) { struct dpu_hw_blk_reg_map *c =3D &ctx->hw; @@ -600,7 +632,13 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->setup_blendstage =3D dpu_hw_ctl_setup_blendstage; ops->get_bitmask_sspp =3D dpu_hw_ctl_get_bitmask_sspp; ops->get_bitmask_mixer =3D dpu_hw_ctl_get_bitmask_mixer; - ops->get_bitmask_dspp =3D dpu_hw_ctl_get_bitmask_dspp; + if (cap & BIT(DPU_CTL_HIERARCHICAL_FLUSH)) { + ops->get_bitmask_dspp =3D dpu_hw_ctl_get_bitmask_dspp_v1; + ops->set_dspp_hierarchical_flush =3D dpu_hw_ctl_set_dspp_hierarchical_fl= ush; + } else { + ops->get_bitmask_dspp =3D dpu_hw_ctl_get_bitmask_dspp; + } + if (cap & BIT(DPU_CTL_FETCH_ACTIVE)) ops->set_active_pipes =3D dpu_hw_ctl_set_fetch_pipe_active; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index ac15444..8ecab91 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -160,6 +160,9 @@ struct dpu_hw_ctl_ops { uint32_t (*get_bitmask_dspp)(struct dpu_hw_ctl *ctx, enum dpu_dspp blk); =20 + void (*set_dspp_hierarchical_flush)(struct dpu_hw_ctl *ctx, + enum dpu_dspp blk, enum dpu_dspp_sub_blk dspp_sub_blk); + /** * Set all blend stages to disabled * @ctx : ctl path ctx pointer diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index bb9cead..561e2ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -166,6 +166,13 @@ enum dpu_dspp { DSPP_MAX }; =20 +enum dpu_dspp_sub_blk{ + DSPP_SUB_PCC =3D 1, + DSPP_SUB_IGC, + DSPP_SUB_GC, + DSPP_SUB_MAX +}; + enum dpu_ctl { CTL_0 =3D 1, CTL_1, --=20 2.7.4