From nobody Wed Apr 15 01:30:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74039C04A68 for ; Thu, 28 Jul 2022 10:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236554AbiG1KpF (ORCPT ); Thu, 28 Jul 2022 06:45:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236260AbiG1Koe (ORCPT ); Thu, 28 Jul 2022 06:44:34 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 885616393F; Thu, 28 Jul 2022 03:44:15 -0700 (PDT) Date: Thu, 28 Jul 2022 10:44:12 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1659005053; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pcK2FycYemp0p8xnnh4tQD3ECrZKCmRiQOVIlWU0c6c=; b=wcqfgkIEBeQl8SVNfqBo3Zpm89HyMSuzUAm2pOQAp7k6E9xBn2x+RPI5a6OVBJQIiEXYyv NTSqdqXVl+kQbu16a5jIule8dLCnY4hF4A+NEAOgpSosBe7XzEclg3GFcHGa9WikVJY1Io 0lFdt2+62go+tDtisQUHdmZowrMNb9OUXwtFNlFeB6indQgTOjNnlk+DpP+SJQg9X0qxlQ sqcl78oD40BfPsD61nMkI6stst9u/75dVgPHWcKIkioI/9znIuhAq129zRIB848jgqW+Id +3LgtCjQEOfPhTt083f/TW0tY67JUFR+gNSA9Puxn/UZ+31dzM1pSPrzE6V3dw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1659005053; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pcK2FycYemp0p8xnnh4tQD3ECrZKCmRiQOVIlWU0c6c=; b=ZM1GkHcyAb7JnJ+ZFnFUfVmROIhabCUuqAq4i/I5TYCL4o6zsUD+G0nyuKpvuTL5MeUf/+ XXfpn0cYNF6ORsCw== From: "tip-bot2 for Claudiu Beznea" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: timers/core] clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resume} Cc: Claudiu Beznea , Daniel Lezcano , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220609094041.1796372-3-claudiu.beznea@microchip.com> References: <20220609094041.1796372-3-claudiu.beznea@microchip.com> MIME-Version: 1.0 Message-ID: <165900505228.15455.4537190505732487501.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the timers/core branch of tip: Commit-ID: b02180e899c9e04ba6efda7bdf36d9ad028c9f4f Gitweb: https://git.kernel.org/tip/b02180e899c9e04ba6efda7bdf36d9ad0= 28c9f4f Author: Claudiu Beznea AuthorDate: Thu, 09 Jun 2022 12:40:40 +03:00 Committer: Daniel Lezcano CommitterDate: Sat, 16 Jul 2022 00:52:37 +02:00 clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resum= e} Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220609094041.1796372-3-claudiu.beznea@mic= rochip.com Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-microchip-pit64b.c | 24 +++---------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clockso= urce/timer-microchip-pit64b.c index b512593..f507056 100644 --- a/drivers/clocksource/timer-microchip-pit64b.c +++ b/drivers/clocksource/timer-microchip-pit64b.c @@ -344,6 +344,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, if (!cs) return -ENOMEM; =20 + mchp_pit64b_resume(timer); mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0); =20 mchp_pit64b_cs_base =3D timer->base; @@ -365,8 +366,7 @@ static int __init mchp_pit64b_init_clksrc(struct mchp_p= it64b_timer *timer, pr_debug("clksrc: Failed to register PIT64B clocksource!\n"); =20 /* Stop timer. */ - writel_relaxed(MCHP_PIT64B_CR_SWRST, - timer->base + MCHP_PIT64B_CR); + mchp_pit64b_suspend(timer); kfree(cs); =20 return ret; @@ -450,19 +450,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, if (ret) goto irq_unmap; =20 - ret =3D clk_prepare_enable(timer.pclk); - if (ret) - goto irq_unmap; - - if (timer.mode & MCHP_PIT64B_MR_SGCLK) { - ret =3D clk_prepare_enable(timer.gclk); - if (ret) - goto pclk_unprepare; - + if (timer.mode & MCHP_PIT64B_MR_SGCLK) clk_rate =3D clk_get_rate(timer.gclk); - } else { + else clk_rate =3D clk_get_rate(timer.pclk); - } clk_rate =3D clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1); =20 if (clkevt) @@ -471,15 +462,10 @@ static int __init mchp_pit64b_dt_init_timer(struct de= vice_node *node, ret =3D mchp_pit64b_init_clksrc(&timer, clk_rate); =20 if (ret) - goto gclk_unprepare; + goto irq_unmap; =20 return 0; =20 -gclk_unprepare: - if (timer.mode & MCHP_PIT64B_MR_SGCLK) - clk_disable_unprepare(timer.gclk); -pclk_unprepare: - clk_disable_unprepare(timer.pclk); irq_unmap: irq_dispose_mapping(irq); io_unmap: