From nobody Wed Apr 15 03:06:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ECD0C19F21 for ; Wed, 27 Jul 2022 08:28:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbiG0I20 (ORCPT ); Wed, 27 Jul 2022 04:28:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229604AbiG0I2X (ORCPT ); Wed, 27 Jul 2022 04:28:23 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA35045067; Wed, 27 Jul 2022 01:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658910502; x=1690446502; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=9n7kZWVjG8ShqPlsZ0DGrZMqYr7JFh+R9oXg6vwp/Zg=; b=caDwy1OFoUBA7gB4l5JNjtLvn+UWLSLhEaG3CnPoL98mk4ohcD11QtL/ EVWsSgO40syWDzCuvYpS6DOnK0dd1PtiCEOYGCCeA9ZYBNff5FNVKx0gw WyLB92xBI+fT/ifeM+OIhFm1gwmld/In63wIk1VLHRPC9C0MIFIxI8LFM U=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Jul 2022 01:28:21 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 01:28:21 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:20 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:17 -0700 From: Satya Priya To: Rob Herring , Bjorn Andersson CC: Douglas Anderson , Stephen Boyd , Andy Gross , , , , Satya Priya , Taniya Das Subject: [PATCH V7 1/5] dt-bindings: clock: Add "qcom,adsp-pil-mode" property Date: Wed, 27 Jul 2022 13:57:53 +0530 Message-ID: <1658910477-6494-2-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> References: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The LPASS Peripheral loader clocks would be used to bring LPASS out of reset, when this property is present. This is a cleanup done to handle overlap of regmap of lpasscc and lpass_aon blocks. As a part of this, remove the "cc" regmap from lpasscc node. Signed-off-by: Satya Priya Signed-off-by: Taniya Das Reviewed-by: Rob Herring Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++-= --- .../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++= ++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml index 47028d7..633887d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml @@ -36,13 +36,11 @@ properties: items: - description: LPASS qdsp6ss register - description: LPASS top-cc register - - description: LPASS cc register =20 reg-names: items: - const: qdsp6ss - const: top_cc - - const: cc =20 required: - compatible @@ -59,8 +57,8 @@ examples: #include clock-controller@3000000 { compatible =3D "qcom,sc7280-lpasscc"; - reg =3D <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>; - reg-names =3D "qdsp6ss", "top_cc", "cc"; + reg =3D <0x03000000 0x40>, <0x03c04000 0x4>; + reg-names =3D "qdsp6ss", "top_cc"; clocks =3D <&gcc GCC_CFG_NOC_LPASS_CLK>; clock-names =3D "iface"; #clock-cells =3D <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorec= c.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.ya= ml index bad9135..5ccfb24 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -41,6 +41,12 @@ properties: reg: maxItems: 1 =20 + qcom,adsp-pil-mode: + description: + Indicates if the LPASS would be brought out of reset using + peripheral loader. + type: boolean + required: - compatible - reg @@ -165,6 +171,7 @@ examples: clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&lpasscore LPASS_CORE_CC_CORE_CLK>; clock-names =3D "bi_tcxo", "bi_tcxo_ao","iface"; + qcom,adsp-pil-mode; #clock-cells =3D <1>; #power-domain-cells =3D <1>; }; --=20 2.7.4 From nobody Wed Apr 15 03:06:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36F95C04A68 for ; Wed, 27 Jul 2022 08:28:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229923AbiG0I2b (ORCPT ); Wed, 27 Jul 2022 04:28:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230401AbiG0I20 (ORCPT ); Wed, 27 Jul 2022 04:28:26 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE02645064; Wed, 27 Jul 2022 01:28:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658910505; x=1690446505; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=dx+V1w4lrq5BxOBMqbomNCog0rYvnxOH+lpnHWblaHU=; b=r/HGy9gky55Ap7jFuMlyJhl3wYqS/WvDXjLU0i2OdVWCMk/szIQ4cTaY U12p2Uj/KsK1cIsUBu/IVHNJJA5tJDJInFJYrh4kqpeILEH4jDHjfX75p 9vtJcTGZ9vxz8ccLPUJSdRPJrzb8f1FiAbAcwWretHfncYhM3DBEmflPv c=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 27 Jul 2022 01:28:24 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 01:28:24 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:24 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:20 -0700 From: Satya Priya To: Rob Herring , Bjorn Andersson CC: Douglas Anderson , Stephen Boyd , Andy Gross , , , , Satya Priya , Taniya Das Subject: [PATCH V7 2/5] clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon Date: Wed, 27 Jul 2022 13:57:54 +0530 Message-ID: <1658910477-6494-3-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> References: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move registration of lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk to lpass_aon_cc_sc7280_probe and register them only if "qcom,adsp-pil-mode" is enabled in the lpass_aon DT node. Signed-off-by: Satya Priya Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 44 ++++++++++++++++++++++++++++++= ++++ drivers/clk/qcom/lpasscc-sc7280.c | 44 ------------------------------= ---- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpas= saudiocc-sc7280.c index 6ab6e5a3..6067328 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -12,6 +12,7 @@ #include #include =20 +#include #include =20 #include "clk-alpha-pll.h" @@ -38,6 +39,32 @@ static const struct pll_vco zonda_vco[] =3D { { 595200000UL, 3600000000UL, 0 }, }; =20 +static struct clk_branch lpass_q6ss_ahbm_clk =3D { + .halt_reg =3D 0x901c, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x901c, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "lpass_q6ss_ahbm_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch lpass_q6ss_ahbs_clk =3D { + .halt_reg =3D 0x9020, + .halt_check =3D BRANCH_HALT_VOTED, + .clkr =3D { + .enable_reg =3D 0x9020, + .enable_mask =3D BIT(0), + .hw.init =3D &(struct clk_init_data){ + .name =3D "lpass_q6ss_ahbs_clk", + .ops =3D &clk_branch2_ops, + }, + }, +}; + /* 1128.96MHz configuration */ static const struct alpha_pll_config lpass_audio_cc_pll_config =3D { .l =3D 0x3a, @@ -614,6 +641,11 @@ static struct gdsc lpass_aon_cc_lpass_audio_hm_gdsc = =3D { .flags =3D RETAIN_FF_ENABLE, }; =20 +static struct clk_regmap *lpass_cc_sc7280_clocks[] =3D { + [LPASS_Q6SS_AHBM_CLK] =3D &lpass_q6ss_ahbm_clk.clkr, + [LPASS_Q6SS_AHBS_CLK] =3D &lpass_q6ss_ahbs_clk.clkr, +}; + static struct clk_regmap *lpass_aon_cc_sc7280_clocks[] =3D { [LPASS_AON_CC_AUDIO_HM_H_CLK] =3D &lpass_aon_cc_audio_hm_h_clk.clkr, [LPASS_AON_CC_VA_MEM0_CLK] =3D &lpass_aon_cc_va_mem0_clk.clkr, @@ -659,6 +691,12 @@ static struct regmap_config lpass_audio_cc_sc7280_regm= ap_config =3D { .fast_io =3D true, }; =20 +static const struct qcom_cc_desc lpass_cc_sc7280_desc =3D { + .config =3D &lpass_audio_cc_sc7280_regmap_config, + .clks =3D lpass_cc_sc7280_clocks, + .num_clks =3D ARRAY_SIZE(lpass_cc_sc7280_clocks), +}; + static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc =3D { .config =3D &lpass_audio_cc_sc7280_regmap_config, .clks =3D lpass_audio_cc_sc7280_clocks, @@ -785,6 +823,12 @@ static int lpass_aon_cc_sc7280_probe(struct platform_d= evice *pdev) if (ret) return ret; =20 + if (of_property_read_bool(pdev->dev.of_node, "qcom,adsp-pil-mode")) { + lpass_audio_cc_sc7280_regmap_config.name =3D "cc"; + desc =3D &lpass_cc_sc7280_desc; + return qcom_cc_probe(pdev, desc); + } + lpass_audio_cc_sc7280_regmap_config.name =3D "lpasscc_aon"; lpass_audio_cc_sc7280_regmap_config.max_register =3D 0xa0008; desc =3D &lpass_aon_cc_sc7280_desc; diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-s= c7280.c index b39ee1c..5c1e17b 100644 --- a/drivers/clk/qcom/lpasscc-sc7280.c +++ b/drivers/clk/qcom/lpasscc-sc7280.c @@ -17,32 +17,6 @@ #include "clk-branch.h" #include "common.h" =20 -static struct clk_branch lpass_q6ss_ahbm_clk =3D { - .halt_reg =3D 0x1c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1c, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "lpass_q6ss_ahbm_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch lpass_q6ss_ahbs_clk =3D { - .halt_reg =3D 0x20, - .halt_check =3D BRANCH_HALT_VOTED, - .clkr =3D { - .enable_reg =3D 0x20, - .enable_mask =3D BIT(0), - .hw.init =3D &(struct clk_init_data){ - .name =3D "lpass_q6ss_ahbs_clk", - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk =3D { .halt_reg =3D 0x0, .halt_check =3D BRANCH_HALT, @@ -105,17 +79,6 @@ static struct regmap_config lpass_regmap_config =3D { .fast_io =3D true, }; =20 -static struct clk_regmap *lpass_cc_sc7280_clocks[] =3D { - [LPASS_Q6SS_AHBM_CLK] =3D &lpass_q6ss_ahbm_clk.clkr, - [LPASS_Q6SS_AHBS_CLK] =3D &lpass_q6ss_ahbs_clk.clkr, -}; - -static const struct qcom_cc_desc lpass_cc_sc7280_desc =3D { - .config =3D &lpass_regmap_config, - .clks =3D lpass_cc_sc7280_clocks, - .num_clks =3D ARRAY_SIZE(lpass_cc_sc7280_clocks), -}; - static struct clk_regmap *lpass_cc_top_sc7280_clocks[] =3D { [LPASS_TOP_CC_LPI_Q6_AXIM_HS_CLK] =3D &lpass_top_cc_lpi_q6_axim_hs_clk.clkr, @@ -169,13 +132,6 @@ static int lpass_cc_sc7280_probe(struct platform_devic= e *pdev) if (ret) goto destroy_pm_clk; =20 - lpass_regmap_config.name =3D "cc"; - desc =3D &lpass_cc_sc7280_desc; - - ret =3D qcom_cc_probe_by_index(pdev, 2, desc); - if (ret) - goto destroy_pm_clk; - return 0; =20 destroy_pm_clk: --=20 2.7.4 From nobody Wed Apr 15 03:06:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF742C04A68 for ; Wed, 27 Jul 2022 08:28:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230026AbiG0I2k (ORCPT ); Wed, 27 Jul 2022 04:28:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230179AbiG0I2c (ORCPT ); Wed, 27 Jul 2022 04:28:32 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9D6245988; Wed, 27 Jul 2022 01:28:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658910509; 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Wed, 27 Jul 2022 01:28:24 -0700 From: Satya Priya To: Rob Herring , Bjorn Andersson CC: Douglas Anderson , Stephen Boyd , Andy Gross , , , , Taniya Das Subject: [PATCH V7 3/5] dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280 Date: Wed, 27 Jul 2022 13:57:55 +0530 Message-ID: <1658910477-6494-4-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> References: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Taniya Das Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks= on SC7280") Acked-by: Rob Herring Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- .../bindings/clock/qcom,sc7280-lpasscorecc.yaml | 19 +++++++++++++++= +--- include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h | 5 +++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorec= c.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.ya= ml index 5ccfb24..f50e284 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -22,6 +22,8 @@ properties: =20 clock-names: true =20 + reg: true + compatible: enum: - qcom,sc7280-lpassaoncc @@ -38,8 +40,8 @@ properties: '#power-domain-cells': const: 1 =20 - reg: - maxItems: 1 + '#reset-cells': + const: 1 =20 qcom,adsp-pil-mode: description: @@ -75,6 +77,11 @@ allOf: items: - const: bi_tcxo - const: lpass_aon_cc_main_rcg_clk_src + + reg: + items: + - description: lpass core cc register + - description: lpass audio csr register - if: properties: compatible: @@ -96,6 +103,8 @@ allOf: - const: bi_tcxo_ao - const: iface =20 + reg: + maxItems: 1 - if: properties: compatible: @@ -114,6 +123,8 @@ allOf: items: - const: bi_tcxo =20 + reg: + maxItems: 1 examples: - | #include @@ -122,13 +133,15 @@ examples: #include lpass_audiocc: clock-controller@3300000 { compatible =3D "qcom,sc7280-lpassaudiocc"; - reg =3D <0x3300000 0x30000>; + reg =3D <0x3300000 0x30000>, + <0x32a9000 0x1000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; clock-names =3D "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; power-domains =3D <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells =3D <1>; #power-domain-cells =3D <1>; + #reset-cells =3D <1>; }; =20 - | diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include= /dt-bindings/clock/qcom,lpassaudiocc-sc7280.h index 20ef2ea..22dcd47 100644 --- a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h @@ -24,6 +24,11 @@ #define LPASS_AUDIO_CC_RX_MCLK_CLK 14 #define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 =20 +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_TX_CGCR 1 +#define LPASS_AUDIO_SWR_WSA_CGCR 2 + /* LPASS_AON_CC clocks */ #define LPASS_AON_CC_PLL 0 #define LPASS_AON_CC_PLL_OUT_EVEN 1 --=20 2.7.4 From nobody Wed Apr 15 03:06:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C685C04A68 for ; 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charset="utf-8" From: Taniya Das Support external mclk to interface external MI2S clocks for SC7280. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks= on SC7280") Acked-by: Rob Herring Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd --- include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h b/include/= dt-bindings/clock/qcom,lpasscorecc-sc7280.h index 28ed2a0..0324c69 100644 --- a/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h @@ -19,6 +19,8 @@ #define LPASS_CORE_CC_LPM_CORE_CLK 9 #define LPASS_CORE_CC_LPM_MEM0_CORE_CLK 10 #define LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK 11 +#define LPASS_CORE_CC_EXT_MCLK0_CLK 12 +#define LPASS_CORE_CC_EXT_MCLK0_CLK_SRC 13 =20 /* LPASS_CORE_CC power domains */ #define LPASS_CORE_CC_LPASS_CORE_HM_GDSC 0 --=20 2.7.4 From nobody Wed Apr 15 03:06:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5CA5C04A68 for ; Wed, 27 Jul 2022 08:28:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229945AbiG0I2r (ORCPT ); Wed, 27 Jul 2022 04:28:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230416AbiG0I2l (ORCPT ); Wed, 27 Jul 2022 04:28:41 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A14E2459AB; Wed, 27 Jul 2022 01:28:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1658910517; x=1690446517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=uzjq6F1SJxmcG6uhBUAR2toFpR/VawnGq4g+FmKSiB8=; b=oZ2ZVcedO+NQkQgqmYZM/8cI/qXwRUU4dvVarKI0KRtlx+3cFiFE8XN6 v7y2ht75DAUhG+kvdSrT5RxLHBdrRD9HKwaopMwsHlxakxHR9i2mz2IoS CpQscnqfRt1w6SW2iArcg6v12AZH5mPpxgv7ejXW1IAFUVLaXtc+7VWrU g=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 27 Jul 2022 01:28:35 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2022 01:28:34 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:34 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Wed, 27 Jul 2022 01:28:31 -0700 From: Satya Priya To: Rob Herring , Bjorn Andersson CC: Douglas Anderson , Stephen Boyd , Andy Gross , , , , Taniya Das Subject: [PATCH V7 5/5] clk: qcom: lpass: Add support for resets & external mclk for SC7280 Date: Wed, 27 Jul 2022 13:57:57 +0530 Message-ID: <1658910477-6494-6-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> References: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Taniya Das The clock gating control for TX/RX/WSA core bus clocks would be required to be reset(moved from hardware control) from audio core driver. Thus add the support for the reset clocks. Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after disable as this clock signal is used by hardware to turn ON memories in LPASS. Also add the external mclk to interface external MI2S. Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock control= ler for SC7280") Signed-off-by: Taniya Das --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 22 +++++++++++++++++++++- drivers/clk/qcom/lpasscorecc-sc7280.c | 33 ++++++++++++++++++++++++++++++= +++ 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpas= saudiocc-sc7280.c index 6067328..063e036 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -23,6 +23,7 @@ #include "clk-regmap-mux.h" #include "common.h" #include "gdsc.h" +#include "reset.h" =20 enum { P_BI_TCXO, @@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = =3D { .parent_data =3D lpass_aon_cc_parent_data_0, .num_parents =3D ARRAY_SIZE(lpass_aon_cc_parent_data_0), .flags =3D CLK_OPS_PARENT_ENABLE, - .ops =3D &clk_rcg2_ops, + .ops =3D &clk_rcg2_shared_ops, }, }; =20 @@ -703,6 +704,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280= _desc =3D { .num_clks =3D ARRAY_SIZE(lpass_audio_cc_sc7280_clocks), }; =20 +static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] =3D { + [LPASS_AUDIO_SWR_RX_CGCR] =3D { 0xa0, 1 }, + [LPASS_AUDIO_SWR_TX_CGCR] =3D { 0xa8, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] =3D { 0xb0, 1 }, +}; + +static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc =3D { + .config =3D &lpass_audio_cc_sc7280_regmap_config, + .resets =3D lpass_audio_cc_sc7280_resets, + .num_resets =3D ARRAY_SIZE(lpass_audio_cc_sc7280_resets), +}; + static const struct of_device_id lpass_audio_cc_sc7280_match_table[] =3D { { .compatible =3D "qcom,sc7280-lpassaudiocc" }, { } @@ -779,6 +792,13 @@ static int lpass_audio_cc_sc7280_probe(struct platform= _device *pdev) return ret; } =20 + ret =3D qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc= ); + if (ret) { + dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n"); + pm_runtime_disable(&pdev->dev); + return ret; + } + pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); pm_runtime_put_sync(&pdev->dev); diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpass= corecc-sc7280.c index 1f1f1bd..6ad19b0 100644 --- a/drivers/clk/qcom/lpasscorecc-sc7280.c +++ b/drivers/clk/qcom/lpasscorecc-sc7280.c @@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = =3D { }, }; =20 +static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src =3D { + .cmd_rcgr =3D 0x20000, + .mnd_width =3D 8, + .hid_width =3D 5, + .parent_map =3D lpass_core_cc_parent_map_0, + .freq_tbl =3D ftbl_lpass_core_cc_ext_if0_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data){ + .name =3D "lpass_core_cc_ext_mclk0_clk_src", + .parent_data =3D lpass_core_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(lpass_core_cc_parent_data_0), + .ops =3D &clk_rcg2_ops, + }, +}; =20 static struct clk_branch lpass_core_cc_core_clk =3D { .halt_reg =3D 0x1f000, @@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_c= lk =3D { }, }; =20 +static struct clk_branch lpass_core_cc_ext_mclk0_clk =3D { + .halt_reg =3D 0x20014, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x20014, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data){ + .name =3D "lpass_core_cc_ext_mclk0_clk", + .parent_hws =3D (const struct clk_hw*[]){ + &lpass_core_cc_ext_mclk0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk =3D { .halt_reg =3D 0x23000, .halt_check =3D BRANCH_HALT_VOTED, @@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[]= =3D { [LPASS_CORE_CC_LPM_CORE_CLK] =3D &lpass_core_cc_lpm_core_clk.clkr, [LPASS_CORE_CC_LPM_MEM0_CORE_CLK] =3D &lpass_core_cc_lpm_mem0_core_clk.cl= kr, [LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] =3D &lpass_core_cc_sysnoc_mport_cor= e_clk.clkr, + [LPASS_CORE_CC_EXT_MCLK0_CLK] =3D &lpass_core_cc_ext_mclk0_clk.clkr, + [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] =3D &lpass_core_cc_ext_mclk0_clk_src.cl= kr, }; =20 static struct regmap_config lpass_core_cc_sc7280_regmap_config =3D { --=20 2.7.4