From nobody Sat Apr 18 01:23:07 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FEADC43334 for ; Tue, 19 Jul 2022 19:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235944AbiGSTFY (ORCPT ); Tue, 19 Jul 2022 15:05:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231549AbiGSTFW (ORCPT ); Tue, 19 Jul 2022 15:05:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B0152C105; Tue, 19 Jul 2022 12:05:20 -0700 (PDT) Date: Tue, 19 Jul 2022 19:05:16 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1658257518; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ur+bosjTdvrAmhdhVF8+GUTIU+bcYGG9cbu/MPrynHM=; b=2Z9BS3jGsAJffUxlpwc0qXZZ/acGveFsHjgCpnFezQD0QQ7mGwpmPQ1k4ZU7LP2KY7Z/xw GLwdSVBzSNq0B/gOZe3/FYJT+zHQd8xZcnQHdafmZONEV8GSti9YprUI+wgaa7n9NZcwVf 8Ozs2ks7EI4yD/P2MPkJT/N3VQO74tyxurbH26doOB2c7pDQtGvDXuzaIeG1MsJWwNL6Uy n0BRP1K7zZ2eTgV9ZkSTn4T4N+BRn6DkSTpfyWftHK6OklbDH3Fthx0gQVzWtCwMRACRe4 Y2WxSpHlVrxxKKq536xKZquXV+9mCS2FIvYAB1xkjyC4Y3m41cHxh20xiElUbw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1658257518; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ur+bosjTdvrAmhdhVF8+GUTIU+bcYGG9cbu/MPrynHM=; b=1/6hfCzq//LpESTB5RzwemFKhADx7+VRmzJkXcjais0rwN8kTiHsY0wslifYHHeW54ET5g WwTmvK16WYkAl8Dw== From: "tip-bot2 for Paolo Bonzini" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/cpu] x86/cpu: Use MSR_IA32_MISC_ENABLE constants Cc: Paolo Bonzini , Borislav Petkov , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220719174714.2410374-1-pbonzini@redhat.com> References: <20220719174714.2410374-1-pbonzini@redhat.com> MIME-Version: 1.0 Message-ID: <165825751659.15455.988965721431093614.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/cpu branch of tip: Commit-ID: 3f2adf00f52b5f2e9e9f23bb5c77608fc9ee297c Gitweb: https://git.kernel.org/tip/3f2adf00f52b5f2e9e9f23bb5c77608fc= 9ee297c Author: Paolo Bonzini AuthorDate: Tue, 19 Jul 2022 13:47:14 -04:00 Committer: Borislav Petkov CommitterDate: Tue, 19 Jul 2022 20:53:10 +02:00 x86/cpu: Use MSR_IA32_MISC_ENABLE constants Instead of the magic numbers 1<<11 and 1<<12 use the constants from msr-index.h. This makes it obvious where those bits of MSR_IA32_MISC_ENABLE are consumed (and in fact that Linux consumes them at all) to simple minds that grep for MSR_IA32_MISC_ENABLE_.*_UNAVAIL. Signed-off-by: Paolo Bonzini Signed-off-by: Borislav Petkov Link: https://lore.kernel.org/r/20220719174714.2410374-1-pbonzini@redhat.com --- arch/x86/kernel/cpu/intel.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 8321c43..a00dd3e 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -647,9 +647,9 @@ static void init_intel(struct cpuinfo_x86 *c) unsigned int l1, l2; =20 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); - if (!(l1 & (1<<11))) + if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)) set_cpu_cap(c, X86_FEATURE_BTS); - if (!(l1 & (1<<12))) + if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL)) set_cpu_cap(c, X86_FEATURE_PEBS); }