From nobody Sat Apr 18 06:01:52 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C35DC43334 for ; Sat, 16 Jul 2022 10:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbiGPKvX (ORCPT ); Sat, 16 Jul 2022 06:51:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229469AbiGPKvW (ORCPT ); Sat, 16 Jul 2022 06:51:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FBFD1261D for ; Sat, 16 Jul 2022 03:51:20 -0700 (PDT) Date: Sat, 16 Jul 2022 10:51:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657968679; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ToVnBR8bVfwYff6uOctrSKz9LEqnHLVISbMa8FmLdY=; b=voCQ6g8S1traEjaju7S1pW9SIMzktpb94gWgQIvr9ePXf3rho2ApjmpAU9A9jWimYTZD1e IQSXgbHKjzQhQBzIMEjeV3J5cPLYDpnqhDu1Q3y9snzdWvbUmsXgRR5x8PqA/wA7i40Ist T0bWek6kMiR6WHxr/VAblJgQDH9JhJBv8g1FWJTKqvKUwctLrHCzLGabQrKOUC2YBmHtil YF7xrFEfD+iOaa9r87631xlfuzzGujCiEgZF+CO0vtJKg6Gf2DVabS+jpFXTGCqfUqrC/V vhwKXJr1P/7Upo7qHOHiEShAzMutG1My7aNDpVqHDgMgo4297yrCrwI+wShxaQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657968679; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ToVnBR8bVfwYff6uOctrSKz9LEqnHLVISbMa8FmLdY=; b=BS76s1S+JeZlFvFCb6oUymYcnogO9pTIdaoJ63E6ouwi/qpKoN00zpFxW/IJ19efWCcyvt ociKcaxfbwWvA4DQ== From: "irqchip-bot for Michael Walle" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] pinctrl: ocelot: Make irq_chip immutable Cc: Michael Walle , Linus Walleij , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220706151553.1580790-2-michael@walle.cc> References: <20220706151553.1580790-2-michael@walle.cc> MIME-Version: 1.0 Message-ID: <165796867790.15455.12863870206141352541.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 51ff93923e21ed2862e83f208706e3ca31d6f409 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/51ff93923e21ed2862e83f208706e3ca31d6f409 Author: Michael Walle AuthorDate: Wed, 06 Jul 2022 17:15:53 +02:00 Committer: Marc Zyngier CommitterDate: Sat, 16 Jul 2022 11:47:45 +01:00 pinctrl: ocelot: Make irq_chip immutable Since recently, the kernel is nagging about mutable irq_chips: [ 2.593426] gpio gpiochip0: (ocelot-gpio): not an immutable chip, please= consider fixing it! Make it const, flag it as IRQCHIP_IMMUTABLE, add the new helper functions and call the appropriate gpiolib functions. Signed-off-by: Michael Walle Acked-by: Linus Walleij Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220706151553.1580790-2-michael@walle.cc --- drivers/pinctrl/pinctrl-ocelot.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-oce= lot.c index 5f4a8c5..425c1a9 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1761,6 +1761,7 @@ static void ocelot_irq_mask(struct irq_data *data) =20 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), BIT(gpio % 32), 0); + gpiochip_disable_irq(chip, gpio); } =20 static void ocelot_irq_unmask(struct irq_data *data) @@ -1769,6 +1770,7 @@ static void ocelot_irq_unmask(struct irq_data *data) struct ocelot_pinctrl *info =3D gpiochip_get_data(chip); unsigned int gpio =3D irqd_to_hwirq(data); =20 + gpiochip_enable_irq(chip, gpio); regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio), BIT(gpio % 32), BIT(gpio % 32)); } @@ -1790,8 +1792,10 @@ static struct irq_chip ocelot_eoi_irqchip =3D { .irq_mask =3D ocelot_irq_mask, .irq_eoi =3D ocelot_irq_ack, .irq_unmask =3D ocelot_irq_unmask, - .flags =3D IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED, + .flags =3D IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED | + IRQCHIP_IMMUTABLE, .irq_set_type =3D ocelot_irq_set_type, + GPIOCHIP_IRQ_RESOURCE_HELPERS }; =20 static struct irq_chip ocelot_irqchip =3D { @@ -1800,6 +1804,8 @@ static struct irq_chip ocelot_irqchip =3D { .irq_ack =3D ocelot_irq_ack, .irq_unmask =3D ocelot_irq_unmask, .irq_set_type =3D ocelot_irq_set_type, + .flags =3D IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS }; =20 static int ocelot_irq_set_type(struct irq_data *data, unsigned int type) @@ -1863,7 +1869,7 @@ static int ocelot_gpiochip_register(struct platform_d= evice *pdev, irq =3D platform_get_irq_optional(pdev, 0); if (irq > 0) { girq =3D &gc->irq; - girq->chip =3D &ocelot_irqchip; + gpio_irq_chip_set_chip(girq, &ocelot_irqchip); girq->parent_handler =3D ocelot_irq_handler; girq->num_parents =3D 1; girq->parents =3D devm_kcalloc(&pdev->dev, 1,