From nobody Sat Apr 18 21:02:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 309C6C433EF for ; Sun, 10 Jul 2022 08:56:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229661AbiGJI4C (ORCPT ); Sun, 10 Jul 2022 04:56:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229638AbiGJIz7 (ORCPT ); Sun, 10 Jul 2022 04:55:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB2B21901F for ; Sun, 10 Jul 2022 01:55:57 -0700 (PDT) Date: Sun, 10 Jul 2022 08:55:55 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657443356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TU6/Bu1V1S4/6yvxMkEVbW5OTfcRXr5oxRrBsJWkqW4=; b=iNwBpvVxBATeNIUk97wpeQIoLimQ/2CE3H4Q0CfpTqiCtvemB8t+kcxDZOgN4Y/OzUgxgW GixiEBXiSZ8ptM3ioPTf4xInRZqgkuYyQVPdd/LEJVy1JlEqNc5koWBxzii6DtnEaP8mUf 3vDvP6fmtFvk+YvhPUzNTAJHQXQGSr9BfXNU0gjyDNR9CAzEBf2InteISo+Y6WLxgq/q/j yNZNbykJCQ2/CfCvFoKcLLx3rqDQ0qBBV9roWusvO4NG21D6r35KUCb660S+RlRQwA3Az8 LARBGllojbdxUbOlw8WIJDGTY4zR8q5Uxhyw/Opsur5BrDn3wr2Bg8pFKVvRUQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657443356; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TU6/Bu1V1S4/6yvxMkEVbW5OTfcRXr5oxRrBsJWkqW4=; b=VtWgUWL9h79wN54Zo+5oc/XmmVPTpqtpt6gEExjkA3OBp+tCiSs9mwXDwIB9jkR7ItPOXM Y27GNmMawfosL0Bg== From: "irqchip-bot for Samuel Holland" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/sifive-plic: Make better use of the effective affinity mask Cc: Samuel Holland , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220701202440.59059-2-samuel@sholland.org> References: <20220701202440.59059-2-samuel@sholland.org> MIME-Version: 1.0 Message-ID: <165744335515.15455.17575115041613134708.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: de078949218242d57f791b63fac87cdb09cb0424 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/de078949218242d57f791b63fac87cdb09cb0424 Author: Samuel Holland AuthorDate: Fri, 01 Jul 2022 15:24:39 -05:00 Committer: Marc Zyngier CommitterDate: Sun, 10 Jul 2022 09:50:04 +01:00 irqchip/sifive-plic: Make better use of the effective affinity mask The PLIC driver already updates the effective affinity mask in its .irq_set_affinity callback. Take advantage of that information to only touch bits (and take spinlocks) for the specific relevant hart contexts. First, make sure the effective affinity mask is set before IRQ startup. Then, since this mask already takes priv->lmask into account, checking that mask later is no longer needed (and handler->present is equivalent to the bit being set in priv->lmask). Finally, when (un)masking or changing affinity, only clear/set the enable bits in the specific old/new context(s). The cpumask operations in plic_irq_unmask() are not needed because they duplicate the code in plic_set_affinity(). Signed-off-by: Samuel Holland Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220701202440.59059-2-samuel@sholland.org --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-sifive-plic.c | 27 +++++++++------------------ 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 462adac..ea7b748 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -531,6 +531,7 @@ config SIFIVE_PLIC bool "SiFive Platform-Level Interrupt Controller" depends on RISCV select IRQ_DOMAIN_HIERARCHY + select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP help This enables support for the PLIC chip found in SiFive (and potentially other) RISC-V systems. The PLIC controls devices diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index b3a36dc..46595e6 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -114,31 +114,18 @@ static inline void plic_irq_toggle(const struct cpuma= sk *mask, for_each_cpu(cpu, mask) { struct plic_handler *handler =3D per_cpu_ptr(&plic_handlers, cpu); =20 - if (handler->present && - cpumask_test_cpu(cpu, &handler->priv->lmask)) - plic_toggle(handler, d->hwirq, enable); + plic_toggle(handler, d->hwirq, enable); } } =20 static void plic_irq_unmask(struct irq_data *d) { - struct cpumask amask; - unsigned int cpu; - struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); - - cpumask_and(&amask, &priv->lmask, cpu_online_mask); - cpu =3D cpumask_any_and(irq_data_get_affinity_mask(d), - &amask); - if (WARN_ON_ONCE(cpu >=3D nr_cpu_ids)) - return; - plic_irq_toggle(cpumask_of(cpu), d, 1); + plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); } =20 static void plic_irq_mask(struct irq_data *d) { - struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); - - plic_irq_toggle(&priv->lmask, d, 0); + plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); } =20 #ifdef CONFIG_SMP @@ -159,11 +146,13 @@ static int plic_set_affinity(struct irq_data *d, if (cpu >=3D nr_cpu_ids) return -EINVAL; =20 - plic_irq_toggle(&priv->lmask, d, 0); - plic_irq_toggle(cpumask_of(cpu), d, !irqd_irq_masked(d)); + plic_irq_mask(d); =20 irq_data_update_effective_affinity(d, cpumask_of(cpu)); =20 + if (!irqd_irq_masked(d)) + plic_irq_unmask(d); + return IRQ_SET_MASK_OK_DONE; } #endif @@ -190,6 +179,7 @@ static struct irq_chip plic_edge_chip =3D { .irq_set_affinity =3D plic_set_affinity, #endif .irq_set_type =3D plic_irq_set_type, + .flags =3D IRQCHIP_AFFINITY_PRE_STARTUP, }; =20 static struct irq_chip plic_chip =3D { @@ -201,6 +191,7 @@ static struct irq_chip plic_chip =3D { .irq_set_affinity =3D plic_set_affinity, #endif .irq_set_type =3D plic_irq_set_type, + .flags =3D IRQCHIP_AFFINITY_PRE_STARTUP, }; =20 static int plic_irq_set_type(struct irq_data *d, unsigned int type)