From nobody Sat Apr 18 21:02:36 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 937FEC433EF for ; Sun, 10 Jul 2022 08:56:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229664AbiGJI4A (ORCPT ); Sun, 10 Jul 2022 04:56:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbiGJIz5 (ORCPT ); Sun, 10 Jul 2022 04:55:57 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C4D1513F69 for ; Sun, 10 Jul 2022 01:55:56 -0700 (PDT) Date: Sun, 10 Jul 2022 08:55:53 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657443355; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=he+6RADLOK76znUYGQLbS8FNYnriXKpKiN4rM7jMSDg=; b=DyxmPIjrv3kDZ2vlXwx6VXuavxZVrmJqme9/arC/7RRSVlZSuJcWmX+glWM9LmR0QxN0/U yjYT4PtxNOV5fI+Gti0k5O9jGcJje2m3MoO69MqSZiu329f6BqSVf5U3RHYf3qBVnv+A/E lsRO/s3eBi1beJAM/uUL1tRmIoS7cUYfu+7aSt4ao59p+Qf+owiQJkRPusZDOgLHD+PsFF xDjN4xMWbfOziBTSbvigvLbrfOnXqaLqt0J1YD5b0mHW5D3EjwYdENFkTlB57+4p7HnILR NwDFhyN0d8SzXXt/rONehUqwNd9kWpbStN4Ml0d/JTTrkeuGLl3DIVNQ+kOGRg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657443355; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=he+6RADLOK76znUYGQLbS8FNYnriXKpKiN4rM7jMSDg=; b=oSD3meEUp7fjGbFn5OjfcxaEYVr4vTpe6ruZORcwhGBj2nrHpG6vFZf8Q6Ecta1FIA8WJ1 oWQurr+xDLQ62sAg== From: "irqchip-bot for Samuel Holland" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/sifive-plic: Separate the enable and mask operations Cc: Samuel Holland , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220701202440.59059-3-samuel@sholland.org> References: <20220701202440.59059-3-samuel@sholland.org> MIME-Version: 1.0 Message-ID: <165744335323.15455.238417515877913725.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: a1706a1c5062e0908528170f853601ed53f428c8 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/a1706a1c5062e0908528170f853601ed53f428c8 Author: Samuel Holland AuthorDate: Fri, 01 Jul 2022 15:24:40 -05:00 Committer: Marc Zyngier CommitterDate: Sun, 10 Jul 2022 09:50:04 +01:00 irqchip/sifive-plic: Separate the enable and mask operations The PLIC has two per-IRQ checks before sending an IRQ to a hart context. First, it checks that the IRQ's priority is nonzero. Then, it checks that the enable bit is set for that combination of IRQ and context. Currently, the PLIC driver sets both the priority value and the enable bit in its (un)mask operations. However, modifying the enable bit is problematic for two reasons: 1) The enable bits are packed, so changes are not atomic and require taking a spinlock. 2) The following requirement from the PLIC spec, which explains the racy (un)mask operations in plic_irq_eoi(): If the completion ID does not match an interrupt source that is currently enabled for the target, the completion is silently ignored. Both of these problems are solved by using the priority value to mask IRQs. Each IRQ has a separate priority register, so writing the priority value is atomic. And since the enable bit remains set while an IRQ is masked, the EOI operation works normally. The enable bits are still used to control the IRQ's affinity. Signed-off-by: Samuel Holland Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220701202440.59059-3-samuel@sholland.org --- drivers/irqchip/irq-sifive-plic.c | 55 ++++++++++++++++++------------ 1 file changed, 34 insertions(+), 21 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 46595e6..ba49381 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -108,9 +108,7 @@ static inline void plic_irq_toggle(const struct cpumask= *mask, struct irq_data *d, int enable) { int cpu; - struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); =20 - writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); for_each_cpu(cpu, mask) { struct plic_handler *handler =3D per_cpu_ptr(&plic_handlers, cpu); =20 @@ -118,16 +116,37 @@ static inline void plic_irq_toggle(const struct cpuma= sk *mask, } } =20 -static void plic_irq_unmask(struct irq_data *d) +static void plic_irq_enable(struct irq_data *d) { plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); } =20 -static void plic_irq_mask(struct irq_data *d) +static void plic_irq_disable(struct irq_data *d) { plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); } =20 +static void plic_irq_unmask(struct irq_data *d) +{ + struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); +} + +static void plic_irq_mask(struct irq_data *d) +{ + struct plic_priv *priv =3D irq_data_get_irq_chip_data(d); + + writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); +} + +static void plic_irq_eoi(struct irq_data *d) +{ + struct plic_handler *handler =3D this_cpu_ptr(&plic_handlers); + + writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); +} + #ifdef CONFIG_SMP static int plic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force) @@ -146,32 +165,21 @@ static int plic_set_affinity(struct irq_data *d, if (cpu >=3D nr_cpu_ids) return -EINVAL; =20 - plic_irq_mask(d); + plic_irq_disable(d); =20 irq_data_update_effective_affinity(d, cpumask_of(cpu)); =20 - if (!irqd_irq_masked(d)) - plic_irq_unmask(d); + if (!irqd_irq_disabled(d)) + plic_irq_enable(d); =20 return IRQ_SET_MASK_OK_DONE; } #endif =20 -static void plic_irq_eoi(struct irq_data *d) -{ - struct plic_handler *handler =3D this_cpu_ptr(&plic_handlers); - - if (irqd_irq_masked(d)) { - plic_irq_unmask(d); - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); - plic_irq_mask(d); - } else { - writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); - } -} - static struct irq_chip plic_edge_chip =3D { .name =3D "SiFive PLIC", + .irq_enable =3D plic_irq_enable, + .irq_disable =3D plic_irq_disable, .irq_ack =3D plic_irq_eoi, .irq_mask =3D plic_irq_mask, .irq_unmask =3D plic_irq_unmask, @@ -184,6 +192,8 @@ static struct irq_chip plic_edge_chip =3D { =20 static struct irq_chip plic_chip =3D { .name =3D "SiFive PLIC", + .irq_enable =3D plic_irq_enable, + .irq_disable =3D plic_irq_disable, .irq_mask =3D plic_irq_mask, .irq_unmask =3D plic_irq_unmask, .irq_eoi =3D plic_irq_eoi, @@ -429,8 +439,11 @@ static int __init __plic_init(struct device_node *node, i * CONTEXT_ENABLE_SIZE; handler->priv =3D priv; done: - for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) + for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) { plic_toggle(handler, hwirq, 0); + writel(1, priv->regs + PRIORITY_BASE + + hwirq * PRIORITY_PER_ID); + } nr_handlers++; }