From nobody Sun Apr 19 02:15:50 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6344C43334 for ; Thu, 7 Jul 2022 08:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235231AbiGGISN (ORCPT ); Thu, 7 Jul 2022 04:18:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235467AbiGGIRi (ORCPT ); Thu, 7 Jul 2022 04:17:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F7344D4F1 for ; Thu, 7 Jul 2022 01:15:53 -0700 (PDT) Date: Thu, 07 Jul 2022 08:15:50 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657181751; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RRD2nHrpMGmkH0i5M7xT9PMwHigsUjma/i1UJRHOxec=; b=3cxV60yc2VQFfadEMOcanBaOaNRMoabMte0/ffxHAr3ZjiMtfJmqliwsvMHSCs5ukPmHTp YDgmiTCvA/MqrBWAsDqinvjQ7wyP9nlh5WNeShG2xvppykFuKLfX99Zy4FTKQxFwkiT2SJ Am8Zu6U4IKqM7f2a3PUCXv+/p8DmR76U7RTztvQ0fXMfwAdxN01f4zy4akGKhcmv0SrLOR v5oqFQ85PySFZOFQkxnq/3qML6ptLHWfTSn0QI9JUFu2iuu+gVIVxOLvJkTNMzhKeI9ct8 9oQtleUDP1shFKIucWCBzfhZLiCArTu8XIRecqT3RkNFO93Xaa2AC51cN9kYOg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657181751; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RRD2nHrpMGmkH0i5M7xT9PMwHigsUjma/i1UJRHOxec=; b=ewQc+3eiBxW9KxJ6yJuQ8nzSsj5ulxW7EjIXOeGzQpgzB88AYpudwM62CeyxMPaBo4rqJ/ /ansUXkXF6Cas8Dw== From: "irqchip-bot for Antonio Borneo" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Read event trigger type from event_trg register Cc: Antonio Borneo , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220606162757.415354-6-antonio.borneo@foss.st.com> References: <20220606162757.415354-6-antonio.borneo@foss.st.com> MIME-Version: 1.0 Message-ID: <165718175019.15455.4071751189569626975.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: ce4ef8f9f2abcf104a5417225cbfe3560e779093 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/ce4ef8f9f2abcf104a5417225cbfe3560e779093 Author: Antonio Borneo AuthorDate: Mon, 06 Jun 2022 18:27:56 +02:00 Committer: Marc Zyngier CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00 irqchip/stm32-exti: Read event trigger type from event_trg register The flag reporting whether an event is 'direct' or 'configurable' is available in the read-only registers EVENT_TRG. Drop this redundant information from the struct stm32_desc_irq and use the proper bit from EVENT_TRG register. On armv7a this patch reduces by 3% the size of the driver, from text data bss dec hex filename 7233 424 4 7661 1ded irq-stm32-exti.o to 6977 424 4 7405 1ced irq-stm32-exti.o Signed-off-by: Antonio Borneo Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220606162757.415354-6-antonio.borneo@foss= .st.com --- drivers/irqchip/irq-stm32-exti.c | 180 ++++++++++++++++-------------- 1 file changed, 96 insertions(+), 84 deletions(-) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-e= xti.c index e8fa91b..0455896 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -34,6 +34,7 @@ struct stm32_exti_bank { u32 swier_ofst; u32 rpr_ofst; u32 fpr_ofst; + u32 trg_ofst; }; =20 #define UNDEF_REG ~0 @@ -41,7 +42,6 @@ struct stm32_exti_bank { struct stm32_desc_irq { u32 exti; u32 irq_parent; - struct irq_chip *chip; }; =20 struct stm32_exti_drv_data { @@ -78,6 +78,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 =3D= { .swier_ofst =3D 0x10, .rpr_ofst =3D 0x14, .fpr_ofst =3D UNDEF_REG, + .trg_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] =3D { @@ -97,6 +98,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 =3D= { .swier_ofst =3D 0x08, .rpr_ofst =3D 0x88, .fpr_ofst =3D UNDEF_REG, + .trg_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b2 =3D { @@ -107,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = =3D { .swier_ofst =3D 0x28, .rpr_ofst =3D 0x98, .fpr_ofst =3D UNDEF_REG, + .trg_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank stm32h7xx_exti_b3 =3D { @@ -117,6 +120,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = =3D { .swier_ofst =3D 0x48, .rpr_ofst =3D 0xA8, .fpr_ofst =3D UNDEF_REG, + .trg_ofst =3D UNDEF_REG, }; =20 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] =3D { @@ -138,6 +142,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = =3D { .swier_ofst =3D 0x08, .rpr_ofst =3D 0x0C, .fpr_ofst =3D 0x10, + .trg_ofst =3D 0x3EC, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b2 =3D { @@ -148,6 +153,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = =3D { .swier_ofst =3D 0x28, .rpr_ofst =3D 0x2C, .fpr_ofst =3D 0x30, + .trg_ofst =3D 0x3E8, }; =20 static const struct stm32_exti_bank stm32mp1_exti_b3 =3D { @@ -158,6 +164,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = =3D { .swier_ofst =3D 0x48, .rpr_ofst =3D 0x4C, .fpr_ofst =3D 0x50, + .trg_ofst =3D 0x3E4, }; =20 static const struct stm32_exti_bank *stm32mp1_exti_banks[] =3D { @@ -170,90 +177,90 @@ static struct irq_chip stm32_exti_h_chip; static struct irq_chip stm32_exti_h_chip_direct; =20 static const struct stm32_desc_irq stm32mp1_desc_irq[] =3D { - { .exti =3D 0, .irq_parent =3D 6, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 1, .irq_parent =3D 7, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 2, .irq_parent =3D 8, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 3, .irq_parent =3D 9, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 4, .irq_parent =3D 10, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 5, .irq_parent =3D 23, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 6, .irq_parent =3D 64, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 7, .irq_parent =3D 65, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 8, .irq_parent =3D 66, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 9, .irq_parent =3D 67, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 10, .irq_parent =3D 40, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 11, .irq_parent =3D 42, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 12, .irq_parent =3D 76, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 13, .irq_parent =3D 77, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 14, .irq_parent =3D 121, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 15, .irq_parent =3D 127, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 16, .irq_parent =3D 1, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 19, .irq_parent =3D 3, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 21, .irq_parent =3D 31, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 22, .irq_parent =3D 33, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 23, .irq_parent =3D 72, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 24, .irq_parent =3D 95, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 25, .irq_parent =3D 107, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 26, .irq_parent =3D 37, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 27, .irq_parent =3D 38, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 28, .irq_parent =3D 39, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 29, .irq_parent =3D 71, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 30, .irq_parent =3D 52, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 31, .irq_parent =3D 53, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 32, .irq_parent =3D 82, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 33, .irq_parent =3D 83, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 47, .irq_parent =3D 93, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 48, .irq_parent =3D 138, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 50, .irq_parent =3D 139, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 52, .irq_parent =3D 140, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 53, .irq_parent =3D 141, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 54, .irq_parent =3D 135, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 61, .irq_parent =3D 100, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 65, .irq_parent =3D 144, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 68, .irq_parent =3D 143, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 70, .irq_parent =3D 62, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 73, .irq_parent =3D 129, .chip =3D &stm32_exti_h_chip }, + { .exti =3D 0, .irq_parent =3D 6 }, + { .exti =3D 1, .irq_parent =3D 7 }, + { .exti =3D 2, .irq_parent =3D 8 }, + { .exti =3D 3, .irq_parent =3D 9 }, + { .exti =3D 4, .irq_parent =3D 10 }, + { .exti =3D 5, .irq_parent =3D 23 }, + { .exti =3D 6, .irq_parent =3D 64 }, + { .exti =3D 7, .irq_parent =3D 65 }, + { .exti =3D 8, .irq_parent =3D 66 }, + { .exti =3D 9, .irq_parent =3D 67 }, + { .exti =3D 10, .irq_parent =3D 40 }, + { .exti =3D 11, .irq_parent =3D 42 }, + { .exti =3D 12, .irq_parent =3D 76 }, + { .exti =3D 13, .irq_parent =3D 77 }, + { .exti =3D 14, .irq_parent =3D 121 }, + { .exti =3D 15, .irq_parent =3D 127 }, + { .exti =3D 16, .irq_parent =3D 1 }, + { .exti =3D 19, .irq_parent =3D 3 }, + { .exti =3D 21, .irq_parent =3D 31 }, + { .exti =3D 22, .irq_parent =3D 33 }, + { .exti =3D 23, .irq_parent =3D 72 }, + { .exti =3D 24, .irq_parent =3D 95 }, + { .exti =3D 25, .irq_parent =3D 107 }, + { .exti =3D 26, .irq_parent =3D 37 }, + { .exti =3D 27, .irq_parent =3D 38 }, + { .exti =3D 28, .irq_parent =3D 39 }, + { .exti =3D 29, .irq_parent =3D 71 }, + { .exti =3D 30, .irq_parent =3D 52 }, + { .exti =3D 31, .irq_parent =3D 53 }, + { .exti =3D 32, .irq_parent =3D 82 }, + { .exti =3D 33, .irq_parent =3D 83 }, + { .exti =3D 47, .irq_parent =3D 93 }, + { .exti =3D 48, .irq_parent =3D 138 }, + { .exti =3D 50, .irq_parent =3D 139 }, + { .exti =3D 52, .irq_parent =3D 140 }, + { .exti =3D 53, .irq_parent =3D 141 }, + { .exti =3D 54, .irq_parent =3D 135 }, + { .exti =3D 61, .irq_parent =3D 100 }, + { .exti =3D 65, .irq_parent =3D 144 }, + { .exti =3D 68, .irq_parent =3D 143 }, + { .exti =3D 70, .irq_parent =3D 62 }, + { .exti =3D 73, .irq_parent =3D 129 }, }; =20 static const struct stm32_desc_irq stm32mp13_desc_irq[] =3D { - { .exti =3D 0, .irq_parent =3D 6, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 1, .irq_parent =3D 7, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 2, .irq_parent =3D 8, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 3, .irq_parent =3D 9, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 4, .irq_parent =3D 10, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 5, .irq_parent =3D 24, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 6, .irq_parent =3D 65, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 7, .irq_parent =3D 66, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 8, .irq_parent =3D 67, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 9, .irq_parent =3D 68, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 10, .irq_parent =3D 41, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 11, .irq_parent =3D 43, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 12, .irq_parent =3D 77, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 13, .irq_parent =3D 78, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 14, .irq_parent =3D 106, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 15, .irq_parent =3D 109, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 16, .irq_parent =3D 1, .chip =3D &stm32_exti_h_chip }, - { .exti =3D 19, .irq_parent =3D 3, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 21, .irq_parent =3D 32, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 22, .irq_parent =3D 34, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 23, .irq_parent =3D 73, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 24, .irq_parent =3D 93, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 25, .irq_parent =3D 114, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 26, .irq_parent =3D 38, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 27, .irq_parent =3D 39, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 28, .irq_parent =3D 40, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 29, .irq_parent =3D 72, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 30, .irq_parent =3D 53, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 31, .irq_parent =3D 54, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 32, .irq_parent =3D 83, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 33, .irq_parent =3D 84, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 44, .irq_parent =3D 96, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 47, .irq_parent =3D 92, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 48, .irq_parent =3D 116, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 50, .irq_parent =3D 117, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 52, .irq_parent =3D 118, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 53, .irq_parent =3D 119, .chip =3D &stm32_exti_h_chip_direct = }, - { .exti =3D 68, .irq_parent =3D 63, .chip =3D &stm32_exti_h_chip_direct }, - { .exti =3D 70, .irq_parent =3D 98, .chip =3D &stm32_exti_h_chip_direct }, + { .exti =3D 0, .irq_parent =3D 6 }, + { .exti =3D 1, .irq_parent =3D 7 }, + { .exti =3D 2, .irq_parent =3D 8 }, + { .exti =3D 3, .irq_parent =3D 9 }, + { .exti =3D 4, .irq_parent =3D 10 }, + { .exti =3D 5, .irq_parent =3D 24 }, + { .exti =3D 6, .irq_parent =3D 65 }, + { .exti =3D 7, .irq_parent =3D 66 }, + { .exti =3D 8, .irq_parent =3D 67 }, + { .exti =3D 9, .irq_parent =3D 68 }, + { .exti =3D 10, .irq_parent =3D 41 }, + { .exti =3D 11, .irq_parent =3D 43 }, + { .exti =3D 12, .irq_parent =3D 77 }, + { .exti =3D 13, .irq_parent =3D 78 }, + { .exti =3D 14, .irq_parent =3D 106 }, + { .exti =3D 15, .irq_parent =3D 109 }, + { .exti =3D 16, .irq_parent =3D 1 }, + { .exti =3D 19, .irq_parent =3D 3 }, + { .exti =3D 21, .irq_parent =3D 32 }, + { .exti =3D 22, .irq_parent =3D 34 }, + { .exti =3D 23, .irq_parent =3D 73 }, + { .exti =3D 24, .irq_parent =3D 93 }, + { .exti =3D 25, .irq_parent =3D 114 }, + { .exti =3D 26, .irq_parent =3D 38 }, + { .exti =3D 27, .irq_parent =3D 39 }, + { .exti =3D 28, .irq_parent =3D 40 }, + { .exti =3D 29, .irq_parent =3D 72 }, + { .exti =3D 30, .irq_parent =3D 53 }, + { .exti =3D 31, .irq_parent =3D 54 }, + { .exti =3D 32, .irq_parent =3D 83 }, + { .exti =3D 33, .irq_parent =3D 84 }, + { .exti =3D 44, .irq_parent =3D 96 }, + { .exti =3D 47, .irq_parent =3D 92 }, + { .exti =3D 48, .irq_parent =3D 116 }, + { .exti =3D 50, .irq_parent =3D 117 }, + { .exti =3D 52, .irq_parent =3D 118 }, + { .exti =3D 53, .irq_parent =3D 119 }, + { .exti =3D 68, .irq_parent =3D 63 }, + { .exti =3D 70, .irq_parent =3D 98 }, }; =20 static const struct stm32_exti_drv_data stm32mp1_drv_data =3D { @@ -711,6 +718,8 @@ static int stm32_exti_h_domain_alloc(struct irq_domain = *dm, struct irq_fwspec p_fwspec; irq_hw_number_t hwirq; int bank; + u32 event_trg; + struct irq_chip *chip; =20 hwirq =3D fwspec->param[0]; if (hwirq >=3D host_data->drv_data->bank_nr * IRQS_PER_BANK) @@ -724,8 +733,11 @@ static int stm32_exti_h_domain_alloc(struct irq_domain= *dm, if (!desc) return -EINVAL; =20 - irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip, - chip_data); + event_trg =3D readl_relaxed(host_data->base + chip_data->reg_bank->trg_of= st); + chip =3D (event_trg & BIT(hwirq % IRQS_PER_BANK)) ? + &stm32_exti_h_chip : &stm32_exti_h_chip_direct; + + irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data); if (desc->irq_parent) { p_fwspec.fwnode =3D dm->parent->fwnode; p_fwspec.param_count =3D 3;