From nobody Sun Apr 19 03:59:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C8B7CCA480 for ; Wed, 6 Jul 2022 11:44:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232935AbiGFLoQ (ORCPT ); Wed, 6 Jul 2022 07:44:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232812AbiGFLoJ (ORCPT ); Wed, 6 Jul 2022 07:44:09 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DB5827FE1; Wed, 6 Jul 2022 04:44:08 -0700 (PDT) Date: Wed, 06 Jul 2022 11:44:05 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1657107846; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WQNDvJM0xfToLKfSGT1GOOqjkWUDf95Dg7dwTQ4Av/s=; b=0FQNE05YSdfPZsbbjsQWmjpS5Vsl31m58ptTs84yOyiK/zb9roN75dPAWLlp4HrAk1z644 1SOSjDq3TQTt/3AwKyhc+xzImefgTmeZfL3cPUH7R2/RuXwutjcUmq642BwxS4AVFRMXaJ itiAvSKvcpOjTyxa2OuXxzQ0qHfWiD6ctIyncUfKPOQiHHyl828DNcwZaAhGcyPMXCsCob jzAosoEcNo8eevKZpjnZ6WezpqeCCfk9GxVTQOi4yqqOHnVXrWF/c9f1+8PwIyxZogwb2q jS8jog6p7CO8psLwv5JTi0wikYphVrQXLNZduB1WXoL57aemCJdXlr5V+jKocA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1657107846; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WQNDvJM0xfToLKfSGT1GOOqjkWUDf95Dg7dwTQ4Av/s=; b=X0NCsTJnsd4ifShsBRjxssvI0j8BjUHHO00U8TWKCUe2NBSx98+lPIENcCfAu9gdFxq3i8 ujl7zvcj+h5iDDBw== From: "tip-bot2 for Kan Liang" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel: Fix PEBS data source encoding for ADL Cc: Kan Liang , "Peter Zijlstra (Intel)" , Andi Kleen , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220629150840.2235741-2-kan.liang@linux.intel.com> References: <20220629150840.2235741-2-kan.liang@linux.intel.com> MIME-Version: 1.0 Message-ID: <165710784534.15455.9349056485349357540.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: ccf170e9d8fdacfe435bbe3749c897c7d86d32f8 Gitweb: https://git.kernel.org/tip/ccf170e9d8fdacfe435bbe3749c897c7d= 86d32f8 Author: Kan Liang AuthorDate: Wed, 29 Jun 2022 08:08:40 -07:00 Committer: Peter Zijlstra CommitterDate: Mon, 04 Jul 2022 09:23:09 +02:00 perf/x86/intel: Fix PEBS data source encoding for ADL The PEBS data source encoding for the e-core is different from the p-core. Add the pebs_data_source[] in the struct x86_hybrid_pmu to store the data source encoding for each type of the core. Add intel_pmu_pebs_data_source_grt() for the e-core. There is nothing changed for the data source encoding of the p-core, which still reuse the intel_pmu_pebs_data_source_skl(). Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support") Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Andi Kleen Link: https://lkml.kernel.org/r/20220629150840.2235741-2-kan.liang@linux.in= tel.com --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/ds.c | 51 ++++++++++++++++++++++++++--------- arch/x86/events/perf_event.h | 6 ++++- 3 files changed, 45 insertions(+), 14 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 07d4a5f..bd8b988 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6241,7 +6241,7 @@ __init int intel_pmu_init(void) x86_pmu.flags |=3D PMU_FL_INSTR_LATENCY; x86_pmu.flags |=3D PMU_FL_MEM_LOADS_AUX; x86_pmu.lbr_pt_coexist =3D true; - intel_pmu_pebs_data_source_skl(false); + intel_pmu_pebs_data_source_adl(); x86_pmu.pebs_latency_data =3D adl_latency_data_small; x86_pmu.num_topdown_events =3D 8; x86_pmu.update_topdown_event =3D adl_update_topdown_event; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index de84385..ba60427 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -94,15 +94,40 @@ void __init intel_pmu_pebs_data_source_nhm(void) pebs_data_source[0x07] =3D OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM= ); } =20 -void __init intel_pmu_pebs_data_source_skl(bool pmem) +static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_s= ource) { u64 pmem_or_l4 =3D pmem ? LEVEL(PMEM) : LEVEL(L4); =20 - pebs_data_source[0x08] =3D OP_LH | pmem_or_l4 | P(SNOOP, HIT); - pebs_data_source[0x09] =3D OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); - pebs_data_source[0x0b] =3D OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); - pebs_data_source[0x0c] =3D OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD= ); - pebs_data_source[0x0d] =3D OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM= ); + data_source[0x08] =3D OP_LH | pmem_or_l4 | P(SNOOP, HIT); + data_source[0x09] =3D OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT); + data_source[0x0b] =3D OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE); + data_source[0x0c] =3D OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD); + data_source[0x0d] =3D OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM); +} + +void __init intel_pmu_pebs_data_source_skl(bool pmem) +{ + __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source); +} + +static void __init intel_pmu_pebs_data_source_grt(u64 *data_source) +{ + data_source[0x05] =3D OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); + data_source[0x06] =3D OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); + data_source[0x08] =3D OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD); +} + +void __init intel_pmu_pebs_data_source_adl(void) +{ + u64 *data_source; + + data_source =3D x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_sou= rce; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + __intel_pmu_pebs_data_source_skl(false, data_source); + + data_source =3D x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_sou= rce; + memcpy(data_source, pebs_data_source, sizeof(pebs_data_source)); + intel_pmu_pebs_data_source_grt(data_source); } =20 static u64 precise_store_data(u64 status) @@ -198,7 +223,7 @@ u64 adl_latency_data_small(struct perf_event *event, u6= 4 status) =20 dse.val =3D status; =20 - val =3D pebs_data_source[dse.ld_dse]; + val =3D hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; =20 /* * For the atom core on ADL, @@ -214,7 +239,7 @@ u64 adl_latency_data_small(struct perf_event *event, u6= 4 status) return val; } =20 -static u64 load_latency_data(u64 status) +static u64 load_latency_data(struct perf_event *event, u64 status) { union intel_x86_pebs_dse dse; u64 val; @@ -224,7 +249,7 @@ static u64 load_latency_data(u64 status) /* * use the mapping table for bit 0-3 */ - val =3D pebs_data_source[dse.ld_dse]; + val =3D hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; =20 /* * Nehalem models do not support TLB, Lock infos @@ -263,7 +288,7 @@ static u64 load_latency_data(u64 status) return val; } =20 -static u64 store_latency_data(u64 status) +static u64 store_latency_data(struct perf_event *event, u64 status) { union intel_x86_pebs_dse dse; u64 val; @@ -273,7 +298,7 @@ static u64 store_latency_data(u64 status) /* * use the mapping table for bit 0-3 */ - val =3D pebs_data_source[dse.st_lat_dse]; + val =3D hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; =20 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked); =20 @@ -1459,9 +1484,9 @@ static u64 get_data_src(struct perf_event *event, u64= aux) bool fst =3D fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC); =20 if (fl & PERF_X86_EVENT_PEBS_LDLAT) - val =3D load_latency_data(aux); + val =3D load_latency_data(event, aux); else if (fl & PERF_X86_EVENT_PEBS_STLAT) - val =3D store_latency_data(aux); + val =3D store_latency_data(event, aux); else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID) val =3D x86_pmu.pebs_latency_data(event, aux); else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC)) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 2d11445..ca2f8bf 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -644,6 +644,8 @@ enum { x86_lbr_exclusive_max, }; =20 +#define PERF_PEBS_DATA_SOURCE_MAX 0x10 + struct x86_hybrid_pmu { struct pmu pmu; const char *name; @@ -671,6 +673,8 @@ struct x86_hybrid_pmu { unsigned int late_ack :1, mid_ack :1, enabled_ack :1; + + u64 pebs_data_source[PERF_PEBS_DATA_SOURCE_MAX]; }; =20 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) @@ -1508,6 +1512,8 @@ void intel_pmu_pebs_data_source_nhm(void); =20 void intel_pmu_pebs_data_source_skl(bool pmem); =20 +void intel_pmu_pebs_data_source_adl(void); + int intel_pmu_setup_lbr_filter(struct perf_event *event); =20 void intel_pt_interrupt(void);