From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00F7EC433EF for ; Fri, 1 Jul 2022 09:47:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236094AbiGAJro (ORCPT ); Fri, 1 Jul 2022 05:47:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236215AbiGAJr3 (ORCPT ); Fri, 1 Jul 2022 05:47:29 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE72D74DE3; Fri, 1 Jul 2022 02:47:28 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 876BE1A13C9; Fri, 1 Jul 2022 11:47:27 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 247C61A13C8; Fri, 1 Jul 2022 11:47:27 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 751151802204; Fri, 1 Jul 2022 17:47:25 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] ASoC: fsl_utils: Add function to handle PLL clock source Date: Fri, 1 Jul 2022 17:32:36 +0800 Message-Id: <1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. Add common function in fsl_utils to handle these two PLL clock source, which are needed by CPU DAI drivers Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_utils.c | 69 +++++++++++++++++++++++++++++++++++++++ sound/soc/fsl/fsl_utils.h | 7 ++++ 2 files changed, 76 insertions(+) diff --git a/sound/soc/fsl/fsl_utils.c b/sound/soc/fsl/fsl_utils.c index 9bab202569af..b75843e31f00 100644 --- a/sound/soc/fsl/fsl_utils.c +++ b/sound/soc/fsl/fsl_utils.c @@ -6,6 +6,8 @@ // // Copyright 2010 Freescale Semiconductor, Inc. =20 +#include +#include #include #include #include @@ -83,6 +85,73 @@ int fsl_asoc_get_dma_channel(struct device_node *ssi_np, } EXPORT_SYMBOL(fsl_asoc_get_dma_channel); =20 +/** + * fsl_asoc_get_pll_clocks - get two PLL clock source + * + * @dev: device pointer + * @pll8k_clk: PLL clock pointer for 8kHz + * @pll11k_clk: PLL clock pointer for 11kHz + * + * This function get two PLL clock source + */ +void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk, + struct clk **pll11k_clk) +{ + *pll8k_clk =3D devm_clk_get(dev, "pll8k"); + if (IS_ERR(*pll8k_clk)) + *pll8k_clk =3D NULL; + + *pll11k_clk =3D devm_clk_get(dev, "pll11k"); + if (IS_ERR(*pll11k_clk)) + *pll11k_clk =3D NULL; +} +EXPORT_SYMBOL(fsl_asoc_get_pll_clocks); + +/** + * fsl_asoc_reparent_pll_clocks - set clock parent if necessary + * + * @dev: device pointer + * @clk: root clock pointer + * @pll8k_clk: PLL clock pointer for 8kHz + * @pll11k_clk: PLL clock pointer for 11kHz + * @ratio: target requency for root clock + * + * This function set root clock parent according to the target ratio + */ +void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk, + struct clk *pll8k_clk, + struct clk *pll11k_clk, u64 ratio) +{ + struct clk *p, *pll =3D 0, *npll =3D 0; + bool reparent =3D false; + int ret =3D 0; + + if (!clk || !pll8k_clk || !pll11k_clk) + return; + + p =3D clk; + while (p && pll8k_clk && pll11k_clk) { + struct clk *pp =3D clk_get_parent(p); + + if (clk_is_match(pp, pll8k_clk) || + clk_is_match(pp, pll11k_clk)) { + pll =3D pp; + break; + } + p =3D pp; + } + + npll =3D (do_div(ratio, 8000) ? pll11k_clk : pll8k_clk); + reparent =3D (pll && !clk_is_match(pll, npll)); + + if (reparent) { + ret =3D clk_set_parent(p, npll); + if (ret < 0) + dev_warn(dev, "failed to set parent %s: %d\n", __clk_get_name(npll), re= t); + } +} +EXPORT_SYMBOL(fsl_asoc_reparent_pll_clocks); + MODULE_AUTHOR("Timur Tabi "); MODULE_DESCRIPTION("Freescale ASoC utility code"); MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/fsl/fsl_utils.h b/sound/soc/fsl/fsl_utils.h index c5dc2a14b492..4d5f3d93bc81 100644 --- a/sound/soc/fsl/fsl_utils.h +++ b/sound/soc/fsl/fsl_utils.h @@ -19,4 +19,11 @@ int fsl_asoc_get_dma_channel(struct device_node *ssi_np,= const char *name, struct snd_soc_dai_link *dai, unsigned int *dma_channel_id, unsigned int *dma_id); + +void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk, + struct clk **pll11k_clk); + +void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk, + struct clk *pll8k_clk, + struct clk *pll11k_clk, u64 ratio); #endif /* _FSL_UTILS_H */ --=20 2.17.1 From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A616C433EF for ; Fri, 1 Jul 2022 09:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236251AbiGAJrz (ORCPT ); Fri, 1 Jul 2022 05:47:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236229AbiGAJra (ORCPT ); Fri, 1 Jul 2022 05:47:30 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6F1974DF4; Fri, 1 Jul 2022 02:47:29 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 5ECDF1A13D2; Fri, 1 Jul 2022 11:47:28 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id F0B121A13C8; Fri, 1 Jul 2022 11:47:27 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id A23E9180222C; Fri, 1 Jul 2022 17:47:26 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] ASoC: fsl_spdif: Add support for PLL switch at runtime. Date: Fri, 1 Jul 2022 17:32:37 +0800 Message-Id: <1656667961-1799-3-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. The patch implements the functionality to select at runtime the appropriate AUDIO PLL as function of audio file rate. As the clock parent may be changed, need to probe txclk according to sample rate again. Signed-off-by: Viorel Suman Signed-off-by: Shengjiu Wang --- sound/soc/fsl/Kconfig | 1 + sound/soc/fsl/fsl_spdif.c | 48 +++++++++++++++++++++++++++++++++++---- 2 files changed, 44 insertions(+), 5 deletions(-) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 10fa38753453..910b8747b6bd 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -59,6 +59,7 @@ config SND_SOC_FSL_SPDIF select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC !=3D n select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC !=3D n && (MXC_TZIC || MXC_AVIC) select BITREVERSE + select SND_SOC_FSL_UTILS help Say Y if you want to add Sony/Philips Digital Interface (SPDIF) support for the Freescale CPUs. diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 0504431792cf..7fc1c96929bb 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -23,6 +23,7 @@ #include =20 #include "fsl_spdif.h" +#include "fsl_utils.h" #include "imx-pcm.h" =20 #define FSL_SPDIF_TXFIFO_WML 0x8 @@ -114,6 +115,8 @@ struct spdif_mixer_control { * @dma_params_rx: DMA parameters for receive channel * @regcache_srpc: regcache for SRPC * @bypass: status of bypass input to output + * @pll8k_clk: PLL clock for the rate of multiply of 8kHz + * @pll11k_clk: PLL clock for the rate of multiply of 11kHz */ struct fsl_spdif_priv { const struct fsl_spdif_soc_data *soc; @@ -137,6 +140,8 @@ struct fsl_spdif_priv { /* regcache for SRPC */ u32 regcache_srpc; bool bypass; + struct clk *pll8k_clk; + struct clk *pll11k_clk; }; =20 static struct fsl_spdif_soc_data fsl_spdif_vf610 =3D { @@ -480,6 +485,8 @@ static int spdif_set_rx_clksrc(struct fsl_spdif_priv *s= pdif_priv, return 0; } =20 +static int fsl_spdif_probe_txclk(struct fsl_spdif_priv *spdif_priv, enum s= pdif_txrate index); + static int spdif_set_sample_rate(struct snd_pcm_substream *substream, int sample_rate) { @@ -528,6 +535,10 @@ static int spdif_set_sample_rate(struct snd_pcm_substr= eam *substream, return -EINVAL; } =20 + ret =3D fsl_spdif_probe_txclk(spdif_priv, rate); + if (ret) + return ret; + clk =3D spdif_priv->txclk_src[rate]; if (clk >=3D STC_TXCLK_SRC_MAX) { dev_err(&pdev->dev, "tx clock source is out of range\n"); @@ -647,6 +658,29 @@ static void fsl_spdif_shutdown(struct snd_pcm_substrea= m *substream, } } =20 +static int spdif_reparent_rootclk(struct fsl_spdif_priv *spdif_priv, unsig= ned int sample_rate) +{ + struct platform_device *pdev =3D spdif_priv->pdev; + struct clk *clk; + int ret; + + /* Reparent clock if required condition is true */ + if (!fsl_spdif_can_set_clk_rate(spdif_priv, STC_TXCLK_SPDIF_ROOT)) + return 0; + + /* Get root clock */ + clk =3D spdif_priv->txclk[STC_TXCLK_SPDIF_ROOT]; + + /* Disable clock first, for it was enabled by pm_runtime */ + clk_disable_unprepare(clk); + fsl_asoc_reparent_pll_clocks(&pdev->dev, clk, spdif_priv->pll8k_clk, + spdif_priv->pll11k_clk, sample_rate); + ret =3D clk_prepare_enable(clk); + if (ret) + return ret; + + return 0; +} static int fsl_spdif_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -659,6 +693,13 @@ static int fsl_spdif_hw_params(struct snd_pcm_substrea= m *substream, int ret =3D 0; =20 if (substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK) { + ret =3D spdif_reparent_rootclk(spdif_priv, sample_rate); + if (ret) { + dev_err(&pdev->dev, "%s: reparent root clk failed: %d\n", + __func__, sample_rate); + return ret; + } + ret =3D spdif_set_sample_rate(substream, sample_rate); if (ret) { dev_err(&pdev->dev, "%s: set sample rate failed: %d\n", @@ -1548,11 +1589,8 @@ static int fsl_spdif_probe(struct platform_device *p= dev) } spdif_priv->rxclk_src =3D DEFAULT_RXCLK_SRC; =20 - for (i =3D 0; i < SPDIF_TXRATE_MAX; i++) { - ret =3D fsl_spdif_probe_txclk(spdif_priv, i); - if (ret) - return ret; - } + fsl_asoc_get_pll_clocks(&pdev->dev, &spdif_priv->pll8k_clk, + &spdif_priv->pll11k_clk); =20 /* Initial spinlock for control data */ ctrl =3D &spdif_priv->fsl_spdif_control; --=20 2.17.1 From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC1B5C433EF for ; Fri, 1 Jul 2022 09:47:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236289AbiGAJrq (ORCPT ); Fri, 1 Jul 2022 05:47:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236234AbiGAJrb (ORCPT ); Fri, 1 Jul 2022 05:47:31 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADC5E74DE3; Fri, 1 Jul 2022 02:47:30 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 611E11A13D6; Fri, 1 Jul 2022 11:47:29 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 290261A13C8; Fri, 1 Jul 2022 11:47:29 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id D030C1802204; Fri, 1 Jul 2022 17:47:27 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] ASoC: fsl_micfil: Add support for PLL switch at runtime Date: Fri, 1 Jul 2022 17:32:38 +0800 Message-Id: <1656667961-1799-4-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. The patch implements the functionality to select at runtime the appropriate AUDIO PLL as function of audio file rate. Signed-off-by: Viorel Suman Signed-off-by: Shengjiu Wang --- sound/soc/fsl/Kconfig | 1 + sound/soc/fsl/fsl_micfil.c | 31 +++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 910b8747b6bd..533937166b4a 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -81,6 +81,7 @@ config SND_SOC_FSL_MICFIL select REGMAP_MMIO select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC !=3D n select SND_SOC_GENERIC_DMAENGINE_PCM + select SND_SOC_FSL_UTILS help Say Y if you want to add Pulse Density Modulation microphone interface (MICFIL) support for NXP. diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c index 18ab80b68752..431278bfbd7b 100644 --- a/sound/soc/fsl/fsl_micfil.c +++ b/sound/soc/fsl/fsl_micfil.c @@ -24,6 +24,7 @@ #include =20 #include "fsl_micfil.h" +#include "fsl_utils.h" =20 #define MICFIL_OSR_DEFAULT 16 =20 @@ -42,6 +43,8 @@ struct fsl_micfil { const struct fsl_micfil_soc_data *soc; struct clk *busclk; struct clk *mclk; + struct clk *pll8k_clk; + struct clk *pll11k_clk; struct snd_dmaengine_dai_dma_data dma_params_rx; struct sdma_peripheral_config sdmacfg; unsigned int dataline; @@ -283,6 +286,27 @@ static int fsl_micfil_trigger(struct snd_pcm_substream= *substream, int cmd, return 0; } =20 +static int fsl_micfil_reparent_rootclk(struct fsl_micfil *micfil, unsigned= int sample_rate) +{ + struct device *dev =3D &micfil->pdev->dev; + u64 ratio =3D sample_rate; + struct clk *clk; + int ret; + + /* Get root clock */ + clk =3D micfil->mclk; + + /* Disable clock first, for it was enabled by pm_runtime */ + clk_disable_unprepare(clk); + fsl_asoc_reparent_pll_clocks(dev, clk, micfil->pll8k_clk, + micfil->pll11k_clk, ratio); + ret =3D clk_prepare_enable(clk); + if (ret) + return ret; + + return 0; +} + static int fsl_micfil_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -306,6 +330,10 @@ static int fsl_micfil_hw_params(struct snd_pcm_substre= am *substream, if (ret) return ret; =20 + ret =3D fsl_micfil_reparent_rootclk(micfil, rate); + if (ret) + return ret; + ret =3D clk_set_rate(micfil->mclk, rate * clk_div * osr * 8); if (ret) return ret; @@ -610,6 +638,9 @@ static int fsl_micfil_probe(struct platform_device *pde= v) return PTR_ERR(micfil->busclk); } =20 + fsl_asoc_get_pll_clocks(&pdev->dev, &micfil->pll8k_clk, + &micfil->pll11k_clk); + /* init regmap */ regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(regs)) --=20 2.17.1 From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DDB4CCA479 for ; Fri, 1 Jul 2022 09:47:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236346AbiGAJrw (ORCPT ); Fri, 1 Jul 2022 05:47:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236240AbiGAJrd (ORCPT ); Fri, 1 Jul 2022 05:47:33 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63E5A74DFB; Fri, 1 Jul 2022 02:47:32 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1A3691A13D5; Fri, 1 Jul 2022 11:47:31 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id ABC4C1A13CF; Fri, 1 Jul 2022 11:47:30 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 09172180222C; Fri, 1 Jul 2022 17:47:28 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] ASoC: fsl_sai: Add support for PLL switch at runtime Date: Fri, 1 Jul 2022 17:32:39 +0800 Message-Id: <1656667961-1799-5-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. The patch implements the functionality to select at runtime the appropriate AUDIO PLL as function of sysclk rate. Signed-off-by: Viorel Suman Signed-off-by: Shengjiu Wang --- sound/soc/fsl/Kconfig | 1 + sound/soc/fsl/fsl_sai.c | 38 ++++++++++++++++++++++++++++++++++++++ sound/soc/fsl/fsl_sai.h | 2 ++ 3 files changed, 41 insertions(+) diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 533937166b4a..614eceda6b9e 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -19,6 +19,7 @@ config SND_SOC_FSL_SAI select REGMAP_MMIO select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC !=3D n select SND_SOC_GENERIC_DMAENGINE_PCM + select SND_SOC_FSL_UTILS help Say Y if you want to add Synchronous Audio Interface (SAI) support for the Freescale CPUs. diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index a0ddaf7e9f60..974ba0780b19 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -23,6 +23,7 @@ #include =20 #include "fsl_sai.h" +#include "fsl_utils.h" #include "imx-pcm.h" =20 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\ @@ -220,14 +221,48 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_d= ai *cpu_dai, return 0; } =20 +static int fsl_sai_set_mclk_rate(struct snd_soc_dai *dai, int clk_id, unsi= gned int freq) +{ + struct fsl_sai *sai =3D snd_soc_dai_get_drvdata(dai); + int ret; + + fsl_asoc_reparent_pll_clocks(dai->dev, sai->mclk_clk[clk_id], + sai->pll8k_clk, sai->pll11k_clk, freq); + + ret =3D clk_set_rate(sai->mclk_clk[clk_id], freq); + if (ret < 0) + dev_err(dai->dev, "failed to set clock rate (%u): %d\n", freq, ret); + + return ret; +} + static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int dir) { + struct fsl_sai *sai =3D snd_soc_dai_get_drvdata(cpu_dai); int ret; =20 if (dir =3D=3D SND_SOC_CLOCK_IN) return 0; =20 + if (freq > 0 && clk_id !=3D FSL_SAI_CLK_BUS) { + if (clk_id < 0 || clk_id >=3D FSL_SAI_MCLK_MAX) { + dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(sai->mclk_clk[clk_id])) { + dev_err(cpu_dai->dev, "Unassigned clock: %d\n", clk_id); + return -EINVAL; + } + + if (sai->mclk_streams =3D=3D 0) { + ret =3D fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq); + if (ret < 0) + return ret; + } + } + ret =3D fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq, true); if (ret) { dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret); @@ -1281,6 +1316,9 @@ static int fsl_sai_probe(struct platform_device *pdev) else sai->mclk_clk[0] =3D sai->bus_clk; =20 + fsl_asoc_get_pll_clocks(&pdev->dev, &sai->pll8k_clk, + &sai->pll11k_clk); + /* read dataline mask for rx and tx*/ ret =3D fsl_sai_read_dlcfg(sai); if (ret < 0) { diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 9bb8ced520c8..17956b5731dc 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -273,6 +273,8 @@ struct fsl_sai { struct regmap *regmap; struct clk *bus_clk; struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; + struct clk *pll8k_clk; + struct clk *pll11k_clk; struct resource *res; =20 bool is_consumer_mode; --=20 2.17.1 From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E45F8C433EF for ; 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Fri, 1 Jul 2022 17:47:30 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Date: Fri, 1 Jul 2022 17:32:40 +0800 Message-Id: <1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add two PLL clock source, they are the parent clocks of root clock one is for 8kHz series rates, another one is for 11kHz series rates. They are optional clocks, if there are such clocks, then driver can switch between them for supporting more accurate rates. Signed-off-by: Shengjiu Wang Acked-by: Rob Herring --- Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Docum= entation/devicetree/bindings/sound/fsl,spdif.yaml index f226ec13167a..1d64e8337aa4 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -58,6 +58,8 @@ properties: slave of the Shared Peripheral Bus and when two or more bus mast= ers (CPU, DMA or DSP) try to access it. This property is optional de= pending on the SoC design. + - description: PLL clock source for 8kHz series rate, optional. + - description: PLL clock source for 11khz series rate, optional. minItems: 9 =20 clock-names: @@ -72,6 +74,8 @@ properties: - const: rxtx6 - const: rxtx7 - const: spba + - const: pll8k + - const: pll11k minItems: 9 =20 big-endian: --=20 2.17.1 From nobody Sun Apr 19 13:43:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B70FC433EF for ; Fri, 1 Jul 2022 09:47:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235550AbiGAJrk (ORCPT ); Fri, 1 Jul 2022 05:47:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236251AbiGAJrf (ORCPT ); Fri, 1 Jul 2022 05:47:35 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A328174DE3; Fri, 1 Jul 2022 02:47:34 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 59C4420139E; Fri, 1 Jul 2022 11:47:33 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 228FB20139A; Fri, 1 Jul 2022 11:47:33 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 6C0A0181D0CA; Fri, 1 Jul 2022 17:47:31 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source Date: Fri, 1 Jul 2022 17:32:41 +0800 Message-Id: <1656667961-1799-7-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> References: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add two PLL clock source, they are the parent clocks of root clock one is for 8kHz series rates, another one is for 11kHz series rates. They are optional clocks, if there are such clocks, then driver can switch between them for supporting more accurate rates. Signed-off-by: Shengjiu Wang Acked-by: Rob Herring --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Document= ation/devicetree/bindings/sound/fsl-sai.txt index 4c66e6a1a533..fbdefc3fade7 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -21,6 +21,9 @@ Required properties: - clock-names : Must include the "bus" for register access and "mclk1", "mclk2", "mclk3" for bit clock and frame clock providing. + "pll8k", "pll11k" are optional, they are the clo= ck + source for root clock, one is for 8kHz series ra= tes + another one is for 11kHz series rates. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. =20 --=20 2.17.1