From nobody Sun Apr 19 17:02:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DE2CCCA480 for ; Wed, 29 Jun 2022 02:20:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229796AbiF2CU1 (ORCPT ); Tue, 28 Jun 2022 22:20:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229477AbiF2CUZ (ORCPT ); Tue, 28 Jun 2022 22:20:25 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADB1024087; Tue, 28 Jun 2022 19:20:23 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id h9-20020a17090a648900b001ecb8596e43so14559945pjj.5; Tue, 28 Jun 2022 19:20:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eznfU5OLKvux3gk+UgnTY7Ig8FiLSf5GcaFaWnp7GUE=; b=Ue6/w6+gHn+7BaHHNO/gaM7l3MTam8H2xkn++ezdQJXMY7Ao5TxSMUlN95sqB9jv4h Rp9H3QKbtpv214j2mUxhHF4ws40uVnUw5N+S3RQLSFKScImIa/2CWLc2GJEQAtF5V+us drypwf+JuQ3EiPxf2zOAe1ZdmME7i+SULxRYdRAbDZ2+R8nkN9lceot75xSDytvfRDKM HA6aaRLy3cl+2HZ6YaRXTp659PwalLtBBd3DOeEu4BiWio25F/FhkKMozQGvscxGauUT 2HBsZWqqF525C85HwvtqSPCnBDTdIb2UDf0d49hikg5WrPquaROs4q/Z4CWbU0suZZXe 6zyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eznfU5OLKvux3gk+UgnTY7Ig8FiLSf5GcaFaWnp7GUE=; b=UK2ZlaAJgRNSTvQbUCZggEM5jFM/GxpxXUG/bPL8Xck4YJ5/Cfx/72BPgbCCAZNhTc j1rX7bJHgxGToZTfYJp6nGhwfnjLKyjR2vNmtuOKTTyTcfeMejQcKc1PB2qBFlvu/nYa 6fwYiWL7WrU0Vmmc4BR2XhbuUjCP+E/Lq8Eg+roAkVvl2d9yEp2B8X04fI9Ug/sDXlxN E3UtyiiPnFLMU0Dqvk/w0WKKawElMiLv/GShjGC1125kYUx7qQtZ9CCVpo1CqRSDuXDc LkMiBb/9xs5VIR2K1nUfeFHtRIC+BfLboIlxoIl95IFJji3NFVSvzZ/Z6wtJ6ObWKolF 65Pg== X-Gm-Message-State: AJIora/YJ/ott/kim4GMSFZKLy9gAzPQcs3vfWG8VNajBrfQFAViiTy8 q0OyEjhFc6efgIgUgl3mpiE= X-Google-Smtp-Source: AGRyM1vb9ADFNmrI6jxmjc/1MicCjRqggaPMl8/Zf755QqIwNNEIkVy365hzvho133v5JhP6NF7tJA== X-Received: by 2002:a17:902:b40a:b0:16a:bca:f591 with SMTP id x10-20020a170902b40a00b0016a0bcaf591mr8010431plr.23.1656469223155; Tue, 28 Jun 2022 19:20:23 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:46a:3e21:914b:bb3e:3e56:4806]) by smtp.gmail.com with ESMTPSA id p26-20020a056a0026da00b005251e2b53acsm10089015pfw.116.2022.06.28.19.20.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jun 2022 19:20:22 -0700 (PDT) From: cy_huang To: jic23@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: lars@metafoo.de, cy_huang@richtek.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: iio: adc: Add rtq6056 adc support Date: Wed, 29 Jun 2022 10:20:11 +0800 Message-Id: <1656469212-12717-2-git-send-email-u0084500@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656469212-12717-1-git-send-email-u0084500@gmail.com> References: <1656469212-12717-1-git-send-email-u0084500@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: ChiYuan Huang Add the documentation for Richtek rtq6056. Signed-off-by: ChiYuan Huang --- Since v2 - Change the resistor property name to be generic 'shunt-resistor-micro-ohm= s'. --- .../bindings/iio/adc/richtek,rtq6056.yaml | 56 ++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/richtek,rtq60= 56.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/richtek,rtq6056.yaml= b/Documentation/devicetree/bindings/iio/adc/richtek,rtq6056.yaml new file mode 100644 index 00000000..fe45d8b --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/richtek,rtq6056.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/richtek,rtq6056.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RTQ6056 Bi-Directional Current and Power Monitor with 16-bit ADC + +maintainers: + - ChiYuan Huang + +description: | + The RTQ6056 is a high accuracy current-sense monitor with I2C and SMBus + interface, and the device provides full information for system by reading + out the loading current and power. + + The device monitors both of the drops across sense resistor and the BUS + voltage, converts into the current in amperes, and power in watts through + internal analog-to-digital converter ADC. The programmable calibration, + adjustable conversion time, and averaging function are also built in for + more design flexibility. + + Datasheet is available at + https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf + +properties: + compatible: + const: richtek,rtq6056 + + reg: + maxItems: 1 + + "#io-channel-cells": + const: 1 + + shunt-resistor-micro-ohms: + description: Shunt IN+/IN- sensing node resistor + +required: + - compatible + - reg + - "#io-channel-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + rtq6056@40 { + compatible =3D "richtek,rtq6056"; + reg =3D <0x40>; + #io-channel-cells =3D <1>; + }; + }; --=20 2.7.4 From nobody Sun Apr 19 17:02:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2035DCCA479 for ; Wed, 29 Jun 2022 02:20:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229558AbiF2CUd (ORCPT ); Tue, 28 Jun 2022 22:20:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229547AbiF2CU3 (ORCPT ); Tue, 28 Jun 2022 22:20:29 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B64B124087; Tue, 28 Jun 2022 19:20:27 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id x4so13730532pfq.2; Tue, 28 Jun 2022 19:20:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LTztRz4hLdo6fxiZS9M8sosySYtV1iMuUC2ne4c7zxE=; b=hUrgo2k6Cw+rr83AHqnwXl86ja/zc8+VNqFRpch/6fJWWLEMQ4x8kysVeZXa45cQUx 5jj6WI6vpfqv6i1QXd8NliYfUDtGEHLroYHcXow3cs9g+6g0yT/f1SBeCYl0QoCJHwNc ARhIJbzJAEPlb5Z9D6AYDRzuWiMk23bbV30lIJfRPk0TT13J+JQqrrmoxVfgdeWaWI6G Q5JpLPKYN3cFMP1m3WBtrpVEHA0UZjND7dynaAS+fLItav1WVKCEcbMHvMrNK8QhlpqD TTuUaa1viSHqB3vfVQpM/OdZxFRr6NgjgOqcMEEOmOcUYjjcaQXGikaqlaphFlYIbLZw LV+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LTztRz4hLdo6fxiZS9M8sosySYtV1iMuUC2ne4c7zxE=; b=iUNPUe2+UzMOwfR7ttmwnnGLQrdv3GoQUAUV/kf0J3Sf2fvcLSpKIPrpF4eC5G5YZj uDg0vyo5NyLtw1k9XtIdySuWtau5JD2gKPft7iXlXrTVm4qLbOE5gs82992rTBeO4kIK 9ffkEnXwb5dS6xm7IX5PXR+MZ+MB0AHURxr6J6jL6TWL+mO4RnC7e8PDg1/mAW9jUdw6 srg9foFvP8yNQN9Ru7qDgQQAwrwQLq4bxdOt4Gkw/BOcU64IOq/m9irwC+MsI+laNG2E 36SddndNDWvGz1Wdy5iB8ia4o15ev9lqYc+jdPw1cnG3ACpXAvbVtdq3WdCFSMx+nlj+ l+KQ== X-Gm-Message-State: AJIora8XNDRh42rK2eHoVZdpPoH3t/wzzzrllo0T1LFxJIT69zEoooID 0MOw5V2PE1i3IH4uMfvRSDc= X-Google-Smtp-Source: AGRyM1tFKy00yjf3wuDFTZ+Kweyof/eIHC5K2VRLyKjLxm2O8/HsRTUJda59ft3PqGFb+1oIHlCtSA== X-Received: by 2002:a63:3c1e:0:b0:40d:2747:4016 with SMTP id j30-20020a633c1e000000b0040d27474016mr939270pga.372.1656469227002; Tue, 28 Jun 2022 19:20:27 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:46a:3e21:914b:bb3e:3e56:4806]) by smtp.gmail.com with ESMTPSA id p26-20020a056a0026da00b005251e2b53acsm10089015pfw.116.2022.06.28.19.20.24 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Jun 2022 19:20:26 -0700 (PDT) From: cy_huang To: jic23@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: lars@metafoo.de, cy_huang@richtek.com, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 2/2] iio: adc: Add rtq6056 support Date: Wed, 29 Jun 2022 10:20:12 +0800 Message-Id: <1656469212-12717-3-git-send-email-u0084500@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1656469212-12717-1-git-send-email-u0084500@gmail.com> References: <1656469212-12717-1-git-send-email-u0084500@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: ChiYuan Huang Add Richtek rtq6056 supporting. It can be used for the system to monitor load current and power with 16-bit resolution. Signed-off-by: ChiYuan Huang --- Since v2 - Rename file from 'rtq6056-adc' to 'rtq6056'. - Refine the ABI, if generic already defined it, remove it and check the ch= annel report unit. - Add copyright text. - include the correct header. - change the property parsing name. - To use iio_chan_spec address field. - Refine each channel separate and shared_by_all. - Use pm_runtime and pm_runtime_autosuspend. - Remove the shutdown callback. From the HW suggestion, it's not recommende= d to use battery as the power supply. - Check all scale unit (voltage->mV, current->mA, power->milliWatt). - Use the read_avail to provide the interface for attribute value list. - Add comma for the last element in the const integer array. - Refine each ADC label text. - In read_label callback, replace snprintf to sysfs_emit. --- .../ABI/testing/sysfs-bus-iio-adc-rtq6056 | 6 + drivers/iio/adc/Kconfig | 15 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rtq6056.c | 670 +++++++++++++++++= ++++ 4 files changed, 692 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-iio-adc-rtq6056 create mode 100644 drivers/iio/adc/rtq6056.c diff --git a/Documentation/ABI/testing/sysfs-bus-iio-adc-rtq6056 b/Document= ation/ABI/testing/sysfs-bus-iio-adc-rtq6056 new file mode 100644 index 00000000..db54343 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-iio-adc-rtq6056 @@ -0,0 +1,6 @@ +What: /sys/bus/iio/devices/iio:deviceX/in_voltage0_integration_time +What: /sys/bus/iio/devices/iio:deviceX/in_voltage1_integration_time +KernelVersion: 5.15.31 +Contact: cy_huang@richtek.com +Description: + Each voltage conversion time in uS diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 48ace74..caebd1a 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -908,6 +908,21 @@ config ROCKCHIP_SARADC To compile this driver as a module, choose M here: the module will be called rockchip_saradc. =20 +config RICHTEK_RTQ6056 + tristate "Richtek RTQ6056 Current and Power Monitor ADC" + depends on I2C + select REGMAP_I2C + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER + help + Say yes here to enable RQT6056 ADC support. + RTQ6056 is a high accuracy current-sense monitor with I2C and SMBus + compatible interface, and the device provides full information for + system by reading out the load current and power. + + This driver can also be built as a module. If so, the module will be + called rtq6056. + config RZG2L_ADC tristate "Renesas RZ/G2L ADC driver" depends on ARCH_RZG2L || COMPILE_TEST diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 39d806f..cda7580 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_QCOM_PM8XXX_XOADC) +=3D qcom-pm8xxx-xoadc.o obj-$(CONFIG_RCAR_GYRO_ADC) +=3D rcar-gyroadc.o obj-$(CONFIG_RN5T618_ADC) +=3D rn5t618-adc.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o +obj-$(CONFIG_RICHTEK_RTQ6056) +=3D rtq6056.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o obj-$(CONFIG_SC27XX_ADC) +=3D sc27xx_adc.o obj-$(CONFIG_SPEAR_ADC) +=3D spear_adc.o diff --git a/drivers/iio/adc/rtq6056.c b/drivers/iio/adc/rtq6056.c new file mode 100644 index 00000000..80b9c5f --- /dev/null +++ b/drivers/iio/adc/rtq6056.c @@ -0,0 +1,670 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022 Richtek Technology Corp. + * + * ChiYuan Huang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define RTQ6056_REG_CONFIG 0x00 +#define RTQ6056_REG_SHUNTVOLT 0x01 +#define RTQ6056_REG_BUSVOLT 0x02 +#define RTQ6056_REG_POWER 0x03 +#define RTQ6056_REG_CURRENT 0x04 +#define RTQ6056_REG_CALIBRATION 0x05 +#define RTQ6056_REG_MASKENABLE 0x06 +#define RTQ6056_REG_ALERTLIMIT 0x07 +#define RTQ6056_REG_MANUFACTID 0xFE +#define RTQ6056_REG_DIEID 0xFF + +#define RTQ6056_VENDOR_ID 0x1214 +#define RTQ6056_DEFAULT_CONFIG 0x4127 +#define RTQ6056_CONT_ALLON 7 + +enum { + RTQ6056_CH_VSHUNT =3D 0, + RTQ6056_CH_VBUS, + RTQ6056_CH_POWER, + RTQ6056_CH_CURRENT, + RTQ6056_MAX_CHANNEL +}; + +enum { + F_OPMODE =3D 0, + F_VSHUNTCT, + F_VBUSCT, + F_AVG, + F_RESET, + F_MAX_FIELDS +}; + +struct rtq6056_priv { + struct device *dev; + struct regmap *regmap; + struct regmap_field *rm_fields[F_MAX_FIELDS]; + u32 shunt_resistor_uohm; + int vshuntct_us; + int vbusct_us; + int avg_sample; +}; + +static const struct reg_field rtq6056_reg_fields[F_MAX_FIELDS] =3D { + [F_OPMODE] =3D REG_FIELD(RTQ6056_REG_CONFIG, 0, 2), + [F_VSHUNTCT] =3D REG_FIELD(RTQ6056_REG_CONFIG, 3, 5), + [F_VBUSCT] =3D REG_FIELD(RTQ6056_REG_CONFIG, 6, 8), + [F_AVG] =3D REG_FIELD(RTQ6056_REG_CONFIG, 9, 11), + [F_RESET] =3D REG_FIELD(RTQ6056_REG_CONFIG, 15, 15), +}; + +static const struct iio_chan_spec rtq6056_channels[RTQ6056_MAX_CHANNEL + 1= ] =3D { + { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .channel =3D 0, + .address =3D RTQ6056_REG_SHUNTVOLT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO), + .scan_index =3D 0, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + }, + { + .type =3D IIO_VOLTAGE, + .indexed =3D 1, + .channel =3D 1, + .address =3D RTQ6056_REG_BUSVOLT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_separate_available =3D BIT(IIO_CHAN_INFO_INT_TIME), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO), + .scan_index =3D 1, + .scan_type =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + }, + { + .type =3D IIO_POWER, + .indexed =3D 1, + .channel =3D 2, + .address =3D RTQ6056_REG_POWER, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO), + .scan_index =3D 2, + .scan_type =3D { + .sign =3D 'u', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + }, + { + .type =3D IIO_CURRENT, + .indexed =3D 1, + .channel =3D 3, + .address =3D RTQ6056_REG_CURRENT, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_RA= TIO), + .scan_index =3D 3, + .scan_type =3D { + .sign =3D 's', + .realbits =3D 16, + .storagebits =3D 16, + .endianness =3D IIO_CPU, + }, + }, + IIO_CHAN_SOFT_TIMESTAMP(RTQ6056_MAX_CHANNEL), +}; + +static int rtq6056_adc_read_channel(struct rtq6056_priv *priv, + struct iio_chan_spec const *ch, + int *val) +{ + struct device *dev =3D priv->dev; + unsigned int addr =3D ch->address; + unsigned int regval; + int ret; + + pm_runtime_get_sync(dev); + + ret =3D regmap_read(priv->regmap, addr, ®val); + if (ret) { + pm_runtime_put(dev); + return ret; + } + + /* Power and VBUS is unsigned 16-bit, others are signed 16-bit */ + if (addr =3D=3D RTQ6056_REG_BUSVOLT || addr =3D=3D RTQ6056_REG_POWER) + *val =3D regval; + else + *val =3D sign_extend32(regval, 16); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put(dev); + + return IIO_VAL_INT; +} + +static int rtq6056_adc_read_scale(struct iio_chan_spec const *ch, int *val, + int *val2) +{ + switch (ch->address) { + case RTQ6056_REG_SHUNTVOLT: + /* VSHUNT lsb 2.5uV */ + *val =3D 2500; + *val2 =3D 1000000000; + return IIO_VAL_FRACTIONAL; + case RTQ6056_REG_BUSVOLT: + /* VBUS lsb 1.25mV */ + *val =3D 1250; + *val2 =3D 1000; + return IIO_VAL_FRACTIONAL; + case RTQ6056_REG_POWER: + /* Power lsb 25mV */ + *val =3D 25; + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +/* + * Conversion time in uS for channel VSHUNT and VBUS. The indices correspo= nd + * with the bit value expected by the chip. And it can be found at + * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf + */ +static const int rtq6056_conv_time_list[] =3D { + 139, 203, 269, 525, 1037, 2061, 4109, 8205, +}; + +static int rtq6056_adc_set_conv_time(struct rtq6056_priv *priv, + struct iio_chan_spec const *ch, + int val) +{ + struct regmap_field *rm_field; + unsigned int selector; + int *ct, ret; + + if (val > 8205 || val < 139) + return -EINVAL; + + if (ch->address =3D=3D RTQ6056_REG_SHUNTVOLT) { + rm_field =3D priv->rm_fields[F_VSHUNTCT]; + ct =3D &priv->vshuntct_us; + } else { + rm_field =3D priv->rm_fields[F_VBUSCT]; + ct =3D &priv->vbusct_us; + } + + selector =3D find_closest(val, rtq6056_conv_time_list, + ARRAY_SIZE(rtq6056_conv_time_list)); + + ret =3D regmap_field_write(rm_field, selector); + if (ret) + return ret; + + *ct =3D rtq6056_conv_time_list[selector]; + + return 0; +} + +/* + * Available averaging rate for rtq6056. The indices correspond with the b= it + * value expected by the chip. And it can be found at + * https://www.richtek.com/assets/product_file/RTQ6056/DSQ6056-00.pdf + */ +static const int rtq6056_avg_sample_list[] =3D { + 1, 4, 16, 64, 128, 256, 512, 1024, +}; + +static int rtq6056_adc_set_average(struct rtq6056_priv *priv, int val) +{ + unsigned int selector; + int ret; + + if (val > 1024 || val < 1) + return -EINVAL; + + selector =3D find_closest(val, rtq6056_avg_sample_list, + ARRAY_SIZE(rtq6056_avg_sample_list)); + + ret =3D regmap_field_write(priv->rm_fields[F_AVG], selector); + if (ret) + return ret; + + priv->avg_sample =3D rtq6056_avg_sample_list[selector]; + + return 0; +} + +static int rtq6056_adc_get_sample_freq(struct rtq6056_priv *priv, int *val) +{ + int sample_time; + + sample_time =3D priv->vshuntct_us + priv->vbusct_us; + sample_time *=3D priv->avg_sample; + + *val =3D DIV_ROUND_UP(1000000, sample_time); + + return IIO_VAL_INT; +} + +static int rtq6056_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + struct rtq6056_priv *priv =3D iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_RAW: + return rtq6056_adc_read_channel(priv, chan, val); + case IIO_CHAN_INFO_SCALE: + return rtq6056_adc_read_scale(chan, val, val2); + case IIO_CHAN_INFO_INT_TIME: + if (chan->address =3D=3D RTQ6056_REG_SHUNTVOLT) + *val =3D priv->vshuntct_us; + else + *val =3D priv->vbusct_us; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D priv->avg_sample; + return IIO_VAL_INT; + case IIO_CHAN_INFO_SAMP_FREQ: + return rtq6056_adc_get_sample_freq(priv, val); + default: + return -EINVAL; + } +} + +static int rtq6056_adc_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, int *length, + long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_INT_TIME: + *vals =3D rtq6056_conv_time_list; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(rtq6056_conv_time_list); + return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D rtq6056_avg_sample_list; + *type =3D IIO_VAL_INT; + *length =3D ARRAY_SIZE(rtq6056_avg_sample_list); + return IIO_AVAIL_LIST; + default: + return -EINVAL; + } +} + +static int rtq6056_adc_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, + int val2, long mask) +{ + struct rtq6056_priv *priv =3D iio_priv(indio_dev); + + if (iio_buffer_enabled(indio_dev)) + return -EBUSY; + + switch (mask) { + case IIO_CHAN_INFO_INT_TIME: + return rtq6056_adc_set_conv_time(priv, chan, val); + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + return rtq6056_adc_set_average(priv, val); + default: + return -EINVAL; + } +} + +static const char *rtq6056_channel_labels[RTQ6056_MAX_CHANNEL] =3D { + [RTQ6056_CH_VSHUNT] =3D "Vshunt", + [RTQ6056_CH_VBUS] =3D "Vbus", + [RTQ6056_CH_POWER] =3D "Power", + [RTQ6056_CH_CURRENT] =3D "Current", +}; + +static int rtq6056_adc_read_label(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + char *label) +{ + return sysfs_emit(label, "%s\n", rtq6056_channel_labels[chan->channel]); +} + +static int rtq6056_set_shunt_resistor(struct rtq6056_priv *priv, + int resistor_uohm) +{ + unsigned int calib_val; + int ret; + + if (resistor_uohm <=3D 0) { + dev_err(priv->dev, "Invalid resistor [%d]\n", resistor_uohm); + return -EINVAL; + } + + /* calibration =3D 5120000 / (Rshunt (uohm) * current lsb (1mA)) */ + calib_val =3D 5120000 / resistor_uohm; + ret =3D regmap_write(priv->regmap, RTQ6056_REG_CALIBRATION, calib_val); + if (ret) + return ret; + + priv->shunt_resistor_uohm =3D resistor_uohm; + + return 0; +} + +static ssize_t shunt_resistor_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct rtq6056_priv *priv =3D iio_priv(dev_to_iio_dev(dev)); + int vals[2] =3D { priv->shunt_resistor_uohm, 1000000 }; + + return iio_format_value(buf, IIO_VAL_FRACTIONAL, 1, vals); +} + +static ssize_t shunt_resistor_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev =3D dev_to_iio_dev(dev); + struct rtq6056_priv *priv =3D iio_priv(indio_dev); + int val, val_fract, ret; + + if (iio_buffer_enabled(indio_dev)) + return -EBUSY; + + ret =3D iio_str_to_fixpoint(buf, 100000, &val, &val_fract); + if (ret) + return ret; + + ret =3D rtq6056_set_shunt_resistor(priv, val * 1000000 + val_fract); + if (ret) + return ret; + + return len; +} + +static IIO_DEVICE_ATTR_RW(shunt_resistor, 0); + +static struct attribute *rtq6056_attributes[] =3D { + &iio_dev_attr_shunt_resistor.dev_attr.attr, + NULL +}; + +static const struct attribute_group rtq6056_attribute_group =3D { + .attrs =3D rtq6056_attributes, +}; + +static const struct iio_info rtq6056_info =3D { + .attrs =3D &rtq6056_attribute_group, + .read_raw =3D rtq6056_adc_read_raw, + .read_avail =3D rtq6056_adc_read_avail, + .write_raw =3D rtq6056_adc_write_raw, + .read_label =3D rtq6056_adc_read_label, +}; + +static irqreturn_t rtq6056_buffer_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf =3D p; + struct iio_dev *indio_dev =3D pf->indio_dev; + struct rtq6056_priv *priv =3D iio_priv(indio_dev); + struct device *dev =3D priv->dev; + struct { + u16 vals[RTQ6056_MAX_CHANNEL]; + int64_t timestamp; + } data __aligned(8); + unsigned int raw; + int i =3D 0, bit, ret; + + memset(&data, 0, sizeof(data)); + + pm_runtime_get_sync(dev); + + for_each_set_bit(bit, indio_dev->active_scan_mask, indio_dev->masklength)= { + unsigned int addr =3D rtq6056_channels[bit].address; + + ret =3D regmap_read(priv->regmap, addr, &raw); + if (ret) + goto out; + + data.vals[i++] =3D raw; + } + + iio_push_to_buffers_with_timestamp(indio_dev, &data, iio_get_time_ns(indi= o_dev)); + +out: + pm_runtime_mark_last_busy(dev); + pm_runtime_put(dev); + + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static bool rtq6056_is_readable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RTQ6056_REG_CONFIG ... RTQ6056_REG_ALERTLIMIT: + case RTQ6056_REG_MANUFACTID ... RTQ6056_REG_DIEID: + return true; + default: + return false; + } +} + +static bool rtq6056_is_writeable_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case RTQ6056_REG_CONFIG: + case RTQ6056_REG_CALIBRATION ... RTQ6056_REG_ALERTLIMIT: + return true; + default: + return false; + } +} + +static const struct regmap_config rtq6056_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 16, + .val_format_endian =3D REGMAP_ENDIAN_BIG, + .max_register =3D RTQ6056_REG_DIEID, + .readable_reg =3D rtq6056_is_readable_reg, + .writeable_reg =3D rtq6056_is_writeable_reg, +}; + +static int rtq6056_probe(struct i2c_client *i2c) +{ + struct iio_dev *indio_dev; + struct rtq6056_priv *priv; + struct device *dev =3D &i2c->dev; + struct regmap *regmap; + unsigned int vendor_id, shunt_resistor_uohm; + int ret; + + if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_WORD_DATA)) + return -EOPNOTSUPP; + + indio_dev =3D devm_iio_device_alloc(dev, sizeof(*priv)); + if (!indio_dev) + return -ENOMEM; + + priv =3D iio_priv(indio_dev); + priv->dev =3D dev; + priv->vshuntct_us =3D priv->vbusct_us =3D 1037; + priv->avg_sample =3D 1; + i2c_set_clientdata(i2c, priv); + + regmap =3D devm_regmap_init_i2c(i2c, &rtq6056_regmap_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "Failed to init regmap\n"); + + priv->regmap =3D regmap; + + ret =3D regmap_read(regmap, RTQ6056_REG_MANUFACTID, &vendor_id); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get manufacturer info\n"); + + if (vendor_id !=3D RTQ6056_VENDOR_ID) + return dev_err_probe(dev, -ENODEV, + "Invalid vendor id 0x%04x\n", vendor_id); + + ret =3D devm_regmap_field_bulk_alloc(dev, regmap, priv->rm_fields, + rtq6056_reg_fields, F_MAX_FIELDS); + if (ret) + return dev_err_probe(dev, ret, "Failed to init regmap field\n"); + + /* + * By default, configure average sample as 1, bus and shunt conversion + * timea as 1037 microsecond, and operating mode to all on. + */ + ret =3D regmap_write(regmap, RTQ6056_REG_CONFIG, RTQ6056_DEFAULT_CONFIG); + if (ret) + return dev_err_probe(dev, ret, + "Failed to enable continuous sensing\n"); + + pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); + pm_runtime_use_autosuspend(dev); + pm_runtime_set_active(dev); + pm_runtime_mark_last_busy(dev); + pm_runtime_enable(dev); + + /* By default, use 2000 micro-ohm resistor */ + shunt_resistor_uohm =3D 2000; + device_property_read_u32(dev, "shunt-resistor-micro-ohms", + &shunt_resistor_uohm); + + ret =3D rtq6056_set_shunt_resistor(priv, shunt_resistor_uohm); + if (ret) { + dev_err(dev, "Failed to init shunt resistor\n"); + goto err_probe; + } + + indio_dev->name =3D "rtq6056"; + indio_dev->modes =3D INDIO_DIRECT_MODE; + indio_dev->channels =3D rtq6056_channels; + indio_dev->num_channels =3D ARRAY_SIZE(rtq6056_channels); + indio_dev->info =3D &rtq6056_info; + + ret =3D devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, + rtq6056_buffer_trigger_handler, + NULL); + if (ret) { + dev_err(dev, "Failed to allocate iio trigger buffer\n"); + goto err_probe; + } + + ret =3D devm_iio_device_register(dev, indio_dev); + if (ret) { + dev_err(dev, "Failed to allocate iio device\n"); + goto err_probe; + } + + return 0; + +err_probe: + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + + return ret; +} + +static int rtq6056_remove(struct i2c_client *i2c) +{ + struct device *dev =3D &i2c->dev; + + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_disable(dev); + pm_runtime_set_suspended(dev); + + return 0; +} + +static int rtq6056_runtime_suspend(struct device *dev) +{ + struct rtq6056_priv *priv =3D dev_get_drvdata(dev); + + /* Configure to shutdown mode */ + return regmap_field_write(priv->rm_fields[F_OPMODE], 0); +} + +static int rtq6056_runtime_resume(struct device *dev) +{ + struct rtq6056_priv *priv =3D dev_get_drvdata(dev); + int sample_rdy_time_us, ret; + + ret =3D regmap_field_write(priv->rm_fields[F_OPMODE], RTQ6056_CONT_ALLON); + if (ret) + return ret; + + sample_rdy_time_us =3D priv->vbusct_us + priv->vshuntct_us; + sample_rdy_time_us *=3D priv->avg_sample; + + usleep_range(sample_rdy_time_us, sample_rdy_time_us + 100); + + return 0; +} + +static const struct dev_pm_ops rtq6056_pm_ops =3D { + SET_RUNTIME_PM_OPS(rtq6056_runtime_suspend, rtq6056_runtime_resume, NULL) +}; + +static const struct of_device_id rtq6056_device_match[] =3D { + { .compatible =3D "richtek,rtq6056", }, + {} +}; +MODULE_DEVICE_TABLE(of, rtq6056_device_match); + +static struct i2c_driver rtq6056_driver =3D { + .driver =3D { + .name =3D "rtq6056", + .of_match_table =3D rtq6056_device_match, + .pm =3D &rtq6056_pm_ops, + }, + .probe_new =3D rtq6056_probe, + .remove =3D rtq6056_remove, +}; +module_i2c_driver(rtq6056_driver); + +MODULE_AUTHOR("ChiYuan Huang "); +MODULE_DESCRIPTION("Richtek RTQ6056 Driver"); +MODULE_LICENSE("GPL v2"); --=20 2.7.4