From nobody Thu Apr 30 09:51:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75A04C433EF for ; Tue, 28 Jun 2022 08:54:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343806AbiF1Iye (ORCPT ); Tue, 28 Jun 2022 04:54:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241584AbiF1Iyc (ORCPT ); Tue, 28 Jun 2022 04:54:32 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E9B42DA80 for ; Tue, 28 Jun 2022 01:54:31 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9F98D2027B3; Tue, 28 Jun 2022 10:54:30 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 66FCA2027C9; Tue, 28 Jun 2022 10:54:30 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3A9FD1802204; Tue, 28 Jun 2022 16:54:29 +0800 (+08) From: Shengjiu Wang To: shengjiu.wang@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, nicoleotsuka@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH] ASoC: fsl_micfil: change micfil default settings Date: Tue, 28 Jun 2022 16:39:49 +0800 Message-Id: <1656405589-29850-1-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Previous default settings resulted in loose dynamic range and low sound level. New default configuration changes: - outgain =3D 2 - quality mode =3D VLOW0 - dc remover =3D bypass Signed-off-by: Irina Patru Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_micfil.c | 22 ++++++++++++++++++---- sound/soc/fsl/fsl_micfil.h | 9 +++++++++ 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c index 25c647ae080a..18ab80b68752 100644 --- a/sound/soc/fsl/fsl_micfil.c +++ b/sound/soc/fsl/fsl_micfil.c @@ -48,6 +48,7 @@ struct fsl_micfil { char name[32]; int irq[MICFIL_IRQ_LINES]; enum quality quality; + int dc_remover; }; =20 struct fsl_micfil_soc_data { @@ -336,12 +337,25 @@ static const struct snd_soc_dai_ops fsl_micfil_dai_op= s =3D { static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai) { struct fsl_micfil *micfil =3D dev_get_drvdata(cpu_dai->dev); - int ret; + struct device *dev =3D cpu_dai->dev; + unsigned int val =3D 0; + int ret, i; + + micfil->quality =3D QUALITY_VLOW0; =20 - micfil->quality =3D QUALITY_MEDIUM; + /* set default gain to 2 */ + regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x22222222); =20 - /* set default gain to max_gain */ - regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777); + /* set DC Remover in bypass mode*/ + for (i =3D 0; i < MICFIL_OUTPUT_CHANNELS; i++) + val |=3D MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i); + ret =3D regmap_update_bits(micfil->regmap, REG_MICFIL_DC_CTRL, + MICFIL_DC_CTRL_CONFIG, val); + if (ret) { + dev_err(dev, "failed to set DC Remover mode bits\n"); + return ret; + } + micfil->dc_remover =3D MICFIL_DC_BYPASS; =20 snd_soc_dai_init_dma_data(cpu_dai, NULL, &micfil->dma_params_rx); diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h index 053caba3caf3..d60285dd07bc 100644 --- a/sound/soc/fsl/fsl_micfil.h +++ b/sound/soc/fsl/fsl_micfil.h @@ -73,6 +73,15 @@ #define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch) #define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8) =20 +/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */ +#define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0) +#define MICFIL_DC_CHX_SHIFT(ch) ((ch) << 1) +#define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) <<= 1)) +#define MICFIL_DC_CUTOFF_21HZ 0 +#define MICFIL_DC_CUTOFF_83HZ 1 +#define MICFIL_DC_CUTOFF_152Hz 2 +#define MICFIL_DC_BYPASS 3 + /* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/ #define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24) #define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16) --=20 2.17.1