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Thu, 16 Jun 2022 07:17:50 -0700 Envelope-to: laurent.pinchart@ideasonboard.com, sam@ravnborg.org, dri-devel@lists.freedesktop.org, airlied@linux.ie, daniel@ffwll.ch, linux-kernel@vger.kernel.org Received: from [172.23.135.119] (port=58106 helo=xhdvgannava41x.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1o1qJg-000507-HJ; Thu, 16 Jun 2022 07:17:50 -0700 From: Venkateshwar Rao Gannavarapu To: , , CC: , , , , Venkateshwar Rao Gannavarapu Subject: [PATCH V2 1/2] dt-bindings: display: xlnx: Add DSI 2.0 Tx subsystem documentation Date: Thu, 16 Jun 2022 19:47:35 +0530 Message-ID: <1655389056-37044-2-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1655389056-37044-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> References: <1655389056-37044-1-git-send-email-venkateshwar.rao.gannavarapu@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: bbed6360-0e93-4720-dcb4-08da4fa3019c X-MS-TrafficTypeDiagnostic: SJ0PR02MB7519:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2022 14:17:55.0104 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bbed6360-0e93-4720-dcb4-08da4fa3019c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT054.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB7519 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch adds dt binding for Xilinx DSI-TX subsystem. The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) based display interface. It supports the interface with the programmable logic (FPGA). Signed-off-by: Venkateshwar Rao Gannavarapu --- .../bindings/display/xlnx/xlnx,dsi-tx.yaml | 101 +++++++++++++++++= ++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/xlnx/xlnx,dsi= -tx.yaml diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yam= l b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml new file mode 100644 index 0000000..644934d --- /dev/null +++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,dsi-tx.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/xlnx/xlnx,dsi-tx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx DSI Transmitter subsystem Device Tree Bindings + +maintainers: + - Venkateshwar Rao Gannavarapu + +description: | + The Xilinx DSI Transmitter Subsystem implements the Mobile Industry + Processor Interface based display interface. It supports the interface + with the programmable logic (FPGA). + + For more details refer to PG238 Xilinx MIPI DSI-V2.0 Tx Subsystem. + +properties: + compatible: + const: xlnx,dsi-tx-v2.0 + + reg: + maxItems: 1 + + clocks: + items: + - description: AXI Lite CPU clock + - description: D-PHY clock + + clock-names: + items: + - const: s_axis_aclk + - const: dphy_clk_200M + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: + This port should be the input endpoint. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + This port should be the output endpoint. + +required: + - "#address-cells" + - "#size-cells" + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + dsi0: dsi_tx@80020000 { + compatible =3D "xlnx,dsi-tx-v2.0"; + reg =3D <0x80020000 0x20000>; + clocks =3D <&misc_clk_0>, <&misc_clk_1>; + clock-names =3D "s_axis_aclk", "dphy_clk_200M"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + mipi_dsi_in: endpoint { + remote-endpoint =3D <&pl_disp>; + }; + }; + + port@1 { + reg =3D <1>; + mipi_dsi_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + + panel@0 { + compatible =3D "auo,b101uan01"; + reg =3D <0>; + port { + panel_in: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + }; + }; + +... -- 1.8.3.1 From nobody Mon Apr 27 06:04:20 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0CD0C43334 for ; Thu, 16 Jun 2022 14:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377491AbiFPOS4 (ORCPT ); Thu, 16 Jun 2022 10:18:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377642AbiFPOSz (ORCPT ); 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2022 14:18:49.7006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72419778-38eb-4a86-88d4-08da4fa32233 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT043.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB3249 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Xilinx MIPI DSI Tx Subsystem soft IP is used to display video data from AXI-4 stream interface. It supports upto 4 lanes, optional register interface for the DPHY and multiple RGB color formats. This is a MIPI-DSI host driver and provides DSI bus for panels. This driver also helps to communicate with its panel using panel framework. Signed-off-by: Venkateshwar Rao Gannavarapu Reported-by: kernel test robot --- drivers/gpu/drm/xlnx/Kconfig | 12 ++ drivers/gpu/drm/xlnx/Makefile | 1 + drivers/gpu/drm/xlnx/xlnx_dsi.c | 429 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 442 insertions(+) create mode 100644 drivers/gpu/drm/xlnx/xlnx_dsi.c diff --git a/drivers/gpu/drm/xlnx/Kconfig b/drivers/gpu/drm/xlnx/Kconfig index f9cf93c..a75bd76 100644 --- a/drivers/gpu/drm/xlnx/Kconfig +++ b/drivers/gpu/drm/xlnx/Kconfig @@ -1,3 +1,15 @@ +config DRM_XLNX_DSI + tristate "Xilinx DRM DSI Subsystem Driver" + depends on ARCH_ZYNQMP || COMPILE_TEST + depends on DRM && OF + select DRM_KMS_HELPER + select DRM_MIPI_DSI + select DRM_PANEL_BRIDGE + help + DRM bridge driver for Xilinx programmable DSI subsystem controller. + choose this option if you hava a Xilinx MIPI-DSI Tx subsytem in + video pipeline. + config DRM_ZYNQMP_DPSUB tristate "ZynqMP DisplayPort Controller Driver" depends on ARCH_ZYNQMP || COMPILE_TEST diff --git a/drivers/gpu/drm/xlnx/Makefile b/drivers/gpu/drm/xlnx/Makefile index 51c24b7..f90849b 100644 --- a/drivers/gpu/drm/xlnx/Makefile +++ b/drivers/gpu/drm/xlnx/Makefile @@ -1,2 +1,3 @@ +obj-$(CONFIG_DRM_XLNX_DSI) +=3D xlnx_dsi.o zynqmp-dpsub-y :=3D zynqmp_disp.o zynqmp_dpsub.o zynqmp_dp.o obj-$(CONFIG_DRM_ZYNQMP_DPSUB) +=3D zynqmp-dpsub.o diff --git a/drivers/gpu/drm/xlnx/xlnx_dsi.c b/drivers/gpu/drm/xlnx/xlnx_ds= i.c new file mode 100644 index 0000000..39d8947 --- /dev/null +++ b/drivers/gpu/drm/xlnx/xlnx_dsi.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA MIPI DSI Tx Controller driver. + * + * Copyright (C) 2022 Xilinx, Inc. + * + * Author: Venkateshwar Rao Gannavarapu + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* DSI Tx IP registers */ +#define XDSI_CCR 0x00 +#define XDSI_CCR_COREENB BIT(0) +#define XDSI_CCR_SOFTRST BIT(1) +#define XDSI_CCR_CRREADY BIT(2) +#define XDSI_CCR_CMDMODE BIT(3) +#define XDSI_CCR_DFIFORST BIT(4) +#define XDSI_CCR_CMDFIFORST BIT(5) +#define XDSI_PCR 0x04 +#define XDSI_PCR_LANES_MASK 3 +#define XDSI_PCR_VIDEOMODE(x) (((x) & 0x3) << 3) +#define XDSI_PCR_VIDEOMODE_MASK GENMASK(4, 3) +#define XDSI_PCR_VIDEOMODE_SHIFT 3 +#define XDSI_PCR_BLLPTYPE(x) ((x) << 5) +#define XDSI_PCR_BLLPMODE(x) ((x) << 6) +#define XDSI_PCR_PIXELFORMAT_MASK GENMASK(12, 11) +#define XDSI_PCR_PIXELFORMAT_SHIFT 11 +#define XDSI_PCR_EOTPENABLE(x) ((x) << 13) +#define XDSI_GIER 0x20 +#define XDSI_ISR 0x24 +#define XDSI_IER 0x28 +#define XDSI_STR 0x2C +#define XDSI_STR_RDY_SHPKT BIT(6) +#define XDSI_STR_RDY_LNGPKT BIT(7) +#define XDSI_STR_DFIFO_FULL BIT(8) +#define XDSI_STR_DFIFO_EMPTY BIT(9) +#define XDSI_STR_WAITFR_DATA BIT(10) +#define XDSI_STR_CMD_EXE_PGS BIT(11) +#define XDSI_STR_CCMD_PROC BIT(12) +#define XDSI_CMD 0x30 +#define XDSI_CMD_QUEUE_PACKET(x) ((x) & GENMASK(23, 0)) +#define XDSI_DFR 0x34 +#define XDSI_TIME1 0x50 +#define XDSI_TIME1_BLLP_BURST(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME1_HSA(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME2 0x54 +#define XDSI_TIME2_VACT(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME2_HACT(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_HACT_MULTIPLIER GENMASK(1, 0) +#define XDSI_TIME3 0x58 +#define XDSI_TIME3_HFP(x) ((x) & GENMASK(15, 0)) +#define XDSI_TIME3_HBP(x) (((x) & GENMASK(15, 0)) << 16) +#define XDSI_TIME4 0x5c +#define XDSI_TIME4_VFP(x) ((x) & GENMASK(7, 0)) +#define XDSI_TIME4_VBP(x) (((x) & GENMASK(7, 0)) << 8) +#define XDSI_TIME4_VSA(x) (((x) & GENMASK(7, 0)) << 16) +#define XDSI_NUM_DATA_T 4 + +/** + * struct xlnx_dsi - Xilinx DSI-TX core + * @bridge: DRM bridge structure + * @dsi_host: DSI host device + * @next_bridge: bridge structure + * @dev: device structure + * @clks: clock source structure + * @iomem: Base address of DSI subsystem + * @mode_flags: DSI operation mode related flags + * @lanes: number of active data lanes supported by DSI controller + * @mul_factor: multiplication factor for HACT timing + * @format: pixel format for video mode of DSI controller + * @device_found: Flag to indicate device presence + */ +struct xlnx_dsi { + struct drm_bridge bridge; + struct mipi_dsi_host dsi_host; + struct drm_bridge *next_bridge; + struct device *dev; + struct clk_bulk_data *clks; + void __iomem *iomem; + unsigned long mode_flags; + u32 lanes; + u32 mul_factor; + enum mipi_dsi_pixel_format format; + bool device_found; +}; + +static const struct clk_bulk_data xdsi_clks[] =3D { + { .id =3D "s_axis_aclk" }, + { .id =3D "dphy_clk_200M" }, +}; + +static inline struct xlnx_dsi *host_to_dsi(struct mipi_dsi_host *host) +{ + return container_of(host, struct xlnx_dsi, dsi_host); +} + +static inline struct xlnx_dsi *bridge_to_dsi(struct drm_bridge *bridge) +{ + return container_of(bridge, struct xlnx_dsi, bridge); +} + +static inline void xlnx_dsi_write(struct xlnx_dsi *dsi, int offset, u32 va= l) +{ + writel(val, dsi->iomem + offset); +} + +static inline u32 xlnx_dsi_read(struct xlnx_dsi *dsi, int offset) +{ + return readl(dsi->iomem + offset); +} + +static int xlnx_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct xlnx_dsi *dsi =3D host_to_dsi(host); + struct device *dev =3D host->dev; + + dsi->mode_flags =3D device->mode_flags; + + if (dsi->lanes !=3D device->lanes) { + dev_err(dsi->dev, "Mismatch of lanes. panel =3D %d, DSI =3D %d\n", + device->lanes, dsi->lanes); + return -EINVAL; + } + + if (dsi->format !=3D device->format) { + dev_err(dsi->dev, "Mismatch of format. panel =3D %d, DSI =3D %d\n", + device->format, dsi->format); + return -EINVAL; + } + + if (!dsi->device_found) { + dsi->next_bridge =3D devm_drm_of_get_bridge(dev, + dev->of_node, 0, 0); + if (IS_ERR(dsi->next_bridge)) + return PTR_ERR(dsi->next_bridge); + drm_bridge_add(&dsi->bridge); + dsi->device_found =3D true; + } + + return 0; +} + +static int xlnx_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct xlnx_dsi *dsi =3D host_to_dsi(host); + + drm_bridge_remove(&dsi->bridge); + return 0; +} + +static const struct mipi_dsi_host_ops xlnx_dsi_ops =3D { + .attach =3D xlnx_dsi_host_attach, + .detach =3D xlnx_dsi_host_detach, +}; + +static void +xlnx_dsi_bridge_disable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct xlnx_dsi *dsi =3D bridge_to_dsi(bridge); + u32 reg =3D xlnx_dsi_read(dsi, XDSI_CCR); + + reg &=3D ~XDSI_CCR_COREENB; + xlnx_dsi_write(dsi, XDSI_CCR, reg); +} + +static void +xlnx_dsi_bridge_enable(struct drm_bridge *bridge, + struct drm_bridge_state *old_bridge_state) +{ + struct xlnx_dsi *dsi =3D bridge_to_dsi(bridge); + struct drm_atomic_state *state =3D old_bridge_state->base.state; + struct drm_connector *connector; + struct drm_crtc *crtc; + const struct drm_crtc_state *crtc_state; + const struct drm_display_mode *mode; + u32 reg, video_mode; + + connector =3D drm_atomic_get_new_connector_for_encoder(state, + bridge->encoder); + crtc =3D drm_atomic_get_new_connector_state(state, connector)->crtc; + crtc_state =3D drm_atomic_get_new_crtc_state(state, crtc); + mode =3D &crtc_state->adjusted_mode; + + reg =3D xlnx_dsi_read(dsi, XDSI_PCR); + video_mode =3D (reg & XDSI_PCR_VIDEOMODE_MASK) >> XDSI_PCR_VIDEOMODE_SHIF= T; + + if (!video_mode && (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) { + reg =3D XDSI_TIME1_HSA(mode->hsync_end - + mode->hsync_start); + xlnx_dsi_write(dsi, XDSI_TIME1, reg); + } + + reg =3D XDSI_TIME4_VFP(mode->vsync_start - mode->vdisplay) | + XDSI_TIME4_VBP(mode->vtotal - mode->vsync_end) | + XDSI_TIME4_VSA(mode->vsync_end - mode->vsync_start); + xlnx_dsi_write(dsi, XDSI_TIME4, reg); + + reg =3D XDSI_TIME3_HFP(mode->hsync_start - mode->hdisplay) | + XDSI_TIME3_HBP(mode->htotal - mode->hsync_end); + xlnx_dsi_write(dsi, XDSI_TIME3, reg); + + reg =3D XDSI_TIME2_HACT(mode->hdisplay * dsi->mul_factor / 100) | + XDSI_TIME2_VACT(mode->vdisplay); + xlnx_dsi_write(dsi->iomem, XDSI_TIME2, reg); + + xlnx_dsi_write(dsi, XDSI_PCR, XDSI_PCR_VIDEOMODE(BIT(0))); + + /* Enable Core */ + reg =3D xlnx_dsi_read(dsi, XDSI_CCR); + reg |=3D XDSI_CCR_COREENB; + xlnx_dsi_write(dsi, XDSI_CCR, reg); +} + +#define MAX_INPUT_SEL_FORMATS 3 +static u32 +*xlnx_dsi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + unsigned int i =3D 0; + + *num_input_fmts =3D 0; + input_fmts =3D kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), GFP_KE= RNEL); + if (!input_fmts) + return NULL; + + switch (output_fmt) { + case MEDIA_BUS_FMT_FIXED: + input_fmts[i++] =3D MEDIA_BUS_FMT_RGB888_1X24; + break; + case MEDIA_BUS_FMT_RGB666_1X18: + input_fmts[i++] =3D MEDIA_BUS_FMT_RGB666_1X18; + break; + case MEDIA_BUS_FMT_RGB565_1X16: + input_fmts[i++] =3D MEDIA_BUS_FMT_RGB565_1X16; + break; + default: /* define */ + } + + *num_input_fmts =3D i; + if (*num_input_fmts =3D=3D 0) { + kfree(input_fmts); + input_fmts =3D NULL; + } + + return input_fmts; +} + +static int xlnx_dsi_bridge_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct xlnx_dsi *dsi =3D bridge_to_dsi(bridge); + + if (!dsi->next_bridge) + return 0; + + /* Attach the next bridge */ + return drm_bridge_attach(bridge->encoder, dsi->next_bridge, bridge, + flags); +} + +static void xlnx_dsi_bridge_detach(struct drm_bridge *bridge) +{ + struct xlnx_dsi *dsi =3D bridge_to_dsi(bridge); + + drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); +} + +static enum drm_mode_status +xlnx_dsi_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if ((mode->hdisplay & XDSI_HACT_MULTIPLIER) !=3D 0) + return MODE_BAD_WIDTH; + + return MODE_OK; +} + +static const struct drm_bridge_funcs xlnx_dsi_bridge_funcs =3D { + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_disable =3D xlnx_dsi_bridge_disable, + .atomic_enable =3D xlnx_dsi_bridge_enable, + .atomic_get_input_bus_fmts =3D xlnx_dsi_bridge_atomic_get_input_bus_= fmts, + .attach =3D xlnx_dsi_bridge_attach, + .detach =3D xlnx_dsi_bridge_detach, + .mode_valid =3D xlnx_dsi_bridge_mode_valid, +}; + +static int xlnx_dsi_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct resource *res; + struct xlnx_dsi *dsi; + int ret; + const int xdsi_mul_fact[XDSI_NUM_DATA_T] =3D {300, 225, 225, 200}; + u32 reg; + + dsi =3D devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + dsi->dev =3D dev; + dsi->clks =3D devm_kmemdup(dev, xdsi_clks, sizeof(xdsi_clks), + GFP_KERNEL); + if (!dsi->clks) + return -ENOMEM; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + dsi->iomem =3D devm_ioremap_resource(dev, res); + if (IS_ERR(dsi->iomem)) + return PTR_ERR(dsi->iomem); + + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(xdsi_clks), dsi->clks); + if (ret) + return ret; + + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(xdsi_clks), dsi->clks); + if (ret) + return ret; + + platform_set_drvdata(pdev, dsi); + dsi->dsi_host.ops =3D &xlnx_dsi_ops; + dsi->dsi_host.dev =3D dev; + + ret =3D mipi_dsi_host_register(&dsi->dsi_host); + if (ret) { + dev_err(dev, "Failed to register MIPI host: %d\n", ret); + goto err_clk_put; + } + + dsi->bridge.driver_private =3D dsi; + dsi->bridge.funcs =3D &xlnx_dsi_bridge_funcs; + dsi->bridge.of_node =3D pdev->dev.of_node; + + reg =3D xlnx_dsi_read(dsi, XDSI_PCR); + dsi->lanes =3D reg & XDSI_PCR_LANES_MASK; + dsi->format =3D (reg & XDSI_PCR_PIXELFORMAT_MASK) >> + XDSI_PCR_PIXELFORMAT_SHIFT; + + if (dsi->lanes > 4 || dsi->lanes < 1) { + dev_err(dsi->dev, "%d invalid lanes\n", dsi->lanes); + return -EINVAL; + } + + if (dsi->format > MIPI_DSI_FMT_RGB565) { + dev_err(dsi->dev, "Invalid xlnx,dsi-data-type string\n"); + return -EINVAL; + } + + /* + * Used as a multiplication factor for HACT based on used + * DSI data type. + * + * e.g. for RGB666_L datatype and 1920x1080 resolution, + * the Hact (WC) would be as follows - + * 1920 pixels * 18 bits per pixel / 8 bits per byte + * =3D 1920 pixels * 2.25 bytes per pixel =3D 4320 bytes. + * + * Data Type - Multiplication factor + * RGB888 - 3 + * RGB666_L - 2.25 +- * RGB666_P - 2.25 + * RGB565 - 2 + * + * Since the multiplication factor is a floating number, + * a 100x multiplication factor is used. + */ + dsi->mul_factor =3D xdsi_mul_fact[dsi->format]; + + dev_dbg(dsi->dev, "DSI controller num lanes =3D %d\n", dsi->lanes); + dev_dbg(dsi->dev, "DSI controller format =3D %d\n", dsi->format); + +err_clk_put: + clk_bulk_disable_unprepare(ARRAY_SIZE(xdsi_clks), dsi->clks); + + return ret; +} + +static int xlnx_dsi_remove(struct platform_device *pdev) +{ + struct xlnx_dsi *dsi =3D platform_get_drvdata(pdev); + + mipi_dsi_host_unregister(&dsi->dsi_host); + clk_bulk_disable_unprepare(ARRAY_SIZE(xdsi_clks), dsi->clks); + + return 0; +} + +static const struct of_device_id xlnx_dsi_of_match[] =3D { + { .compatible =3D "xlnx,dsi-tx-v2.0"}, + { } +}; +MODULE_DEVICE_TABLE(of, xlnx_dsi_of_match); + +static struct platform_driver dsi_driver =3D { + .probe =3D xlnx_dsi_probe, + .remove =3D xlnx_dsi_remove, + .driver =3D { + .name =3D "xlnx-dsi", + .of_match_table =3D xlnx_dsi_of_match, + }, +}; + +module_platform_driver(dsi_driver); + +MODULE_AUTHOR("Venkateshwar Rao Gannavarapu "); +MODULE_DESCRIPTION("Xilinx MIPI DSI host controller driver"); +MODULE_LICENSE("GPL"); -- 1.8.3.1