From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 501FFC43334 for ; Tue, 14 Jun 2022 04:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351258AbiFNEZv (ORCPT ); Tue, 14 Jun 2022 00:25:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349068AbiFNEZf (ORCPT ); Tue, 14 Jun 2022 00:25:35 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D48CF2AC76; Mon, 13 Jun 2022 21:25:31 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 3DB13202719; Tue, 14 Jun 2022 06:25:30 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E85B8202718; Tue, 14 Jun 2022 06:25:29 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 0E88B180219B; Tue, 14 Jun 2022 12:25:27 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] ASoC: fsl_sai: Add PDM daifmt support Date: Tue, 14 Jun 2022 12:11:18 +0800 Message-Id: <1655179884-12278-2-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PDM format is used for 1-bit stream, so clear the FBT and SYWD, and the each dataline only has one channel data. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_sai.c | 17 +++++++++++++++-- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 4f5bd9597c74..d11ee3b6f163 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -224,6 +224,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *c= pu_dai, if (!sai->is_lsb_first) val_cr4 |=3D FSL_SAI_CR4_MF; =20 + sai->is_pdm_mode =3D false; /* DAI mode */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: @@ -262,6 +263,11 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *= cpu_dai, val_cr2 |=3D FSL_SAI_CR2_BCP; sai->is_dsp_mode =3D true; break; + case SND_SOC_DAIFMT_PDM: + val_cr2 |=3D FSL_SAI_CR2_BCP; + val_cr4 &=3D ~FSL_SAI_CR4_MF; + sai->is_pdm_mode =3D true; + break; case SND_SOC_DAIFMT_RIGHT_J: /* To be done */ default: @@ -470,6 +476,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream = *substream, =20 pins =3D DIV_ROUND_UP(channels, slots); =20 + /* + * PDM mode, channels are independent + * each channels are on one dataline/FIFO. + */ + if (sai->is_pdm_mode) + pins =3D channels; + if (!sai->is_consumer_mode) { if (sai->bclk_ratio) ret =3D fsl_sai_set_bclk(cpu_dai, tx, @@ -492,13 +505,13 @@ static int fsl_sai_hw_params(struct snd_pcm_substream= *substream, } } =20 - if (!sai->is_dsp_mode) + if (!sai->is_dsp_mode && !sai->is_pdm_mode) val_cr4 |=3D FSL_SAI_CR4_SYWD(slot_width); =20 val_cr5 |=3D FSL_SAI_CR5_WNW(slot_width); val_cr5 |=3D FSL_SAI_CR5_W0W(slot_width); =20 - if (sai->is_lsb_first) + if (sai->is_lsb_first || sai->is_pdm_mode) val_cr5 |=3D FSL_SAI_CR5_FBT(0); else val_cr5 |=3D FSL_SAI_CR5_FBT(word_width - 1); diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 1c8f5ca07f9d..bc2a86a413e1 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -259,6 +259,7 @@ struct fsl_sai { bool is_consumer_mode; bool is_lsb_first; bool is_dsp_mode; + bool is_pdm_mode; bool synchronous[2]; =20 unsigned int mclk_id[2]; --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CB6ACCA47E for ; Tue, 14 Jun 2022 04:25:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350270AbiFNEZl (ORCPT ); Tue, 14 Jun 2022 00:25:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344415AbiFNEZf (ORCPT ); Tue, 14 Jun 2022 00:25:35 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AD862AE2E; Mon, 13 Jun 2022 21:25:32 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id EE18B1A2664; Tue, 14 Jun 2022 06:25:30 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A49061A2676; Tue, 14 Jun 2022 06:25:30 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 3BD3D180222A; Tue, 14 Jun 2022 12:25:29 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] ASoC: fsl_sai: Add DSD bit format support Date: Tue, 14 Jun 2022 12:11:19 +0800 Message-Id: <1655179884-12278-3-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Support DSD_U8, DSD_U16_LE, DSD_U32_LE. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_sai.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index bc2a86a413e1..e28a49ce12ef 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -11,7 +11,10 @@ #define FSL_SAI_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ SNDRV_PCM_FMTBIT_S20_3LE |\ SNDRV_PCM_FMTBIT_S24_LE |\ - SNDRV_PCM_FMTBIT_S32_LE) + SNDRV_PCM_FMTBIT_S32_LE |\ + SNDRV_PCM_FMTBIT_DSD_U8 |\ + SNDRV_PCM_FMTBIT_DSD_U16_LE |\ + SNDRV_PCM_FMTBIT_DSD_U32_LE) =20 /* SAI Register Map Register */ #define FSL_SAI_VERID 0x00 /* SAI Version ID Register */ --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8CBEC43334 for ; Tue, 14 Jun 2022 04:26:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351321AbiFNE0M (ORCPT ); Tue, 14 Jun 2022 00:26:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349712AbiFNEZf (ORCPT ); Tue, 14 Jun 2022 00:25:35 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C7B02AC52; Mon, 13 Jun 2022 21:25:34 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A215C2026FE; Tue, 14 Jun 2022 06:25:32 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 57D96202717; Tue, 14 Jun 2022 06:25:32 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 720D8180219B; Tue, 14 Jun 2022 12:25:30 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] ASoC: fsl_sai: Add support for more sample rates Date: Tue, 14 Jun 2022 12:11:20 +0800 Message-Id: <1655179884-12278-4-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for more sample rates, because PDM format bitstream has higher sample rates. for example DSD512 format, the bit clock is 22.5792MHz, if the word width is U8_LE, then the max sample rate is 2822400. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_sai.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index d11ee3b6f163..9d2828b55c07 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -30,7 +30,8 @@ static const unsigned int fsl_sai_rates[] =3D { 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 64000, - 88200, 96000, 176400, 192000 + 88200, 96000, 176400, 192000, 352800, + 384000, 705600, 768000, 1411200, 2822400, }; =20 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = =3D { @@ -763,7 +764,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = =3D { .channels_min =3D 1, .channels_max =3D 32, .rate_min =3D 8000, - .rate_max =3D 192000, + .rate_max =3D 2822400, .rates =3D SNDRV_PCM_RATE_KNOT, .formats =3D FSL_SAI_FORMATS, }, @@ -772,7 +773,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = =3D { .channels_min =3D 1, .channels_max =3D 32, .rate_min =3D 8000, - .rate_max =3D 192000, + .rate_max =3D 2822400, .rates =3D SNDRV_PCM_RATE_KNOT, .formats =3D FSL_SAI_FORMATS, }, --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68972C433EF for ; Tue, 14 Jun 2022 04:26:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351450AbiFNE0A (ORCPT ); Tue, 14 Jun 2022 00:26:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350441AbiFNEZg (ORCPT ); Tue, 14 Jun 2022 00:25:36 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 57F6A2A73C; Mon, 13 Jun 2022 21:25:35 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 16D731A2684; Tue, 14 Jun 2022 06:25:34 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 845B71A2674; Tue, 14 Jun 2022 06:25:33 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 9F004180222A; Tue, 14 Jun 2022 12:25:31 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] ASoc: fsl_sai: Add pinctrl operation for PDM and DSD Date: Tue, 14 Jun 2022 12:11:21 +0800 Message-Id: <1655179884-12278-5-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With DSD format, the pinctrl is different compare with I2S format, because one dataline only has one channel data, and the codec always mux the LRCLK pin to DSD data line, and on i.MX8MQ the BCLK pin can route to codec on DSD case for the MCLK is too high. Add pinctrl operation that the pinctrl can be switched on runtime according to the I2S format or DSD format Signed-off-by: Viorel Suman Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_sai.c | 70 +++++++++++++++++++++++++++++++++++------ sound/soc/fsl/fsl_sai.h | 2 ++ 2 files changed, 63 insertions(+), 9 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 9d2828b55c07..ddfe28cb7df0 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,31 @@ static inline bool fsl_sai_dir_is_synced(struct fsl_sai = *sai, int dir) return !sai->synchronous[dir] && sai->synchronous[adir]; } =20 +static struct pinctrl_state *fsl_sai_get_pins_state(struct fsl_sai *sai, u= 32 bclk) +{ + struct pinctrl_state *state =3D 0; + + if (sai->is_pdm_mode) { + /* DSD512@44.1kHz, DSD512@48kHz */ + if (bclk >=3D 22579200) + state =3D pinctrl_lookup_state(sai->pinctrl, "dsd512"); + + /* Get default DSD state */ + if (IS_ERR_OR_NULL(state)) + state =3D pinctrl_lookup_state(sai->pinctrl, "dsd"); + } else { + /* 706k32b2c, 768k32b2c, etc */ + if (bclk >=3D 45158400) + state =3D pinctrl_lookup_state(sai->pinctrl, "pcm_b2m"); + } + + /* Get default state */ + if (IS_ERR_OR_NULL(state)) + state =3D pinctrl_lookup_state(sai->pinctrl, "default"); + + return state; +} + static irqreturn_t fsl_sai_isr(int irq, void *devid) { struct fsl_sai *sai =3D (struct fsl_sai *)devid; @@ -466,7 +492,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *= substream, u32 slots =3D (channels =3D=3D 1) ? 2 : channels; u32 slot_width =3D word_width; int adir =3D tx ? RX : TX; - u32 pins; + u32 pins, bclk; int ret; =20 if (sai->slots) @@ -484,15 +510,21 @@ static int fsl_sai_hw_params(struct snd_pcm_substream= *substream, if (sai->is_pdm_mode) pins =3D channels; =20 + bclk =3D params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots= * slot_width); + + if (!IS_ERR_OR_NULL(sai->pinctrl)) { + sai->pins_state =3D fsl_sai_get_pins_state(sai, bclk); + if (!IS_ERR_OR_NULL(sai->pins_state)) { + ret =3D pinctrl_select_state(sai->pinctrl, sai->pins_state); + if (ret) { + dev_err(cpu_dai->dev, "failed to set proper pins state: %d\n", ret); + return ret; + } + } + } + if (!sai->is_consumer_mode) { - if (sai->bclk_ratio) - ret =3D fsl_sai_set_bclk(cpu_dai, tx, - sai->bclk_ratio * - params_rate(params)); - else - ret =3D fsl_sai_set_bclk(cpu_dai, tx, - slots * slot_width * - params_rate(params)); + ret =3D fsl_sai_set_bclk(cpu_dai, tx, bclk); if (ret) return ret; =20 @@ -757,6 +789,23 @@ static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_d= ai) return 0; } =20 +static int fsl_sai_dai_resume(struct snd_soc_component *component) +{ + struct fsl_sai *sai =3D snd_soc_component_get_drvdata(component); + struct device *dev =3D &sai->pdev->dev; + int ret; + + if (!IS_ERR_OR_NULL(sai->pinctrl) && !IS_ERR_OR_NULL(sai->pins_state)) { + ret =3D pinctrl_select_state(sai->pinctrl, sai->pins_state); + if (ret) { + dev_err(dev, "failed to set proper pins state: %d\n", ret); + return ret; + } + } + + return 0; +} + static struct snd_soc_dai_driver fsl_sai_dai_template =3D { .probe =3D fsl_sai_dai_probe, .playback =3D { @@ -782,6 +831,7 @@ static struct snd_soc_dai_driver fsl_sai_dai_template = =3D { =20 static const struct snd_soc_component_driver fsl_component =3D { .name =3D "fsl-sai", + .resume =3D fsl_sai_dai_resume, }; =20 static struct reg_default fsl_sai_reg_defaults_ofs0[] =3D { @@ -1147,6 +1197,8 @@ static int fsl_sai_probe(struct platform_device *pdev) sai->dma_params_rx.maxburst =3D FSL_SAI_MAXBURST_RX; sai->dma_params_tx.maxburst =3D FSL_SAI_MAXBURST_TX; =20 + sai->pinctrl =3D devm_pinctrl_get(&pdev->dev); + platform_set_drvdata(pdev, sai); pm_runtime_enable(dev); if (!pm_runtime_enabled(dev)) { diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index e28a49ce12ef..c0b6bc42fc3c 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -278,6 +278,8 @@ struct fsl_sai { struct fsl_sai_verid verid; struct fsl_sai_param param; struct pm_qos_request pm_qos_req; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_state; }; =20 #define TX 1 --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44B88C433EF for ; Tue, 14 Jun 2022 04:25:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351147AbiFNEZx (ORCPT ); Tue, 14 Jun 2022 00:25:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44432 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346694AbiFNEZh (ORCPT ); Tue, 14 Jun 2022 00:25:37 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B5422AC66; Mon, 13 Jun 2022 21:25:36 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 07F54202710; Tue, 14 Jun 2022 06:25:35 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B1A13202717; Tue, 14 Jun 2022 06:25:34 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id CC104180219B; Tue, 14 Jun 2022 12:25:32 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] ASoC: fsl_sai: Move res variable to be global Date: Tue, 14 Jun 2022 12:11:22 +0800 Message-Id: <1655179884-12278-6-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The resource info need to be accessed by hw_params() function for multi fifo case, the start address may be not the FIFO0. So move it to be global first. Signed-off-by: Shengjiu Wang --- sound/soc/fsl/fsl_sai.c | 7 +++---- sound/soc/fsl/fsl_sai.h | 1 + 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index ddfe28cb7df0..86aa0baba848 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -1077,7 +1077,6 @@ static int fsl_sai_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct fsl_sai *sai; struct regmap *gpr; - struct resource *res; void __iomem *base; char tmp[8]; int irq, ret, i; @@ -1092,7 +1091,7 @@ static int fsl_sai_probe(struct platform_device *pdev) =20 sai->is_lsb_first =3D of_property_read_bool(np, "lsb-first"); =20 - base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &sai->res); if (IS_ERR(base)) return PTR_ERR(base); =20 @@ -1192,8 +1191,8 @@ static int fsl_sai_probe(struct platform_device *pdev) MCLK_DIR(index)); } =20 - sai->dma_params_rx.addr =3D res->start + FSL_SAI_RDR0; - sai->dma_params_tx.addr =3D res->start + FSL_SAI_TDR0; + sai->dma_params_rx.addr =3D sai->res->start + FSL_SAI_RDR0; + sai->dma_params_tx.addr =3D sai->res->start + FSL_SAI_TDR0; sai->dma_params_rx.maxburst =3D FSL_SAI_MAXBURST_RX; sai->dma_params_tx.maxburst =3D FSL_SAI_MAXBURST_TX; =20 diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index c0b6bc42fc3c..4d657edc9c9f 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -258,6 +258,7 @@ struct fsl_sai { struct regmap *regmap; struct clk *bus_clk; struct clk *mclk_clk[FSL_SAI_MCLK_MAX]; + struct resource *res; =20 bool is_consumer_mode; bool is_lsb_first; --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BB7CC433EF for ; Tue, 14 Jun 2022 04:26:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351658AbiFNE0G (ORCPT ); Tue, 14 Jun 2022 00:26:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347106AbiFNEZi (ORCPT ); Tue, 14 Jun 2022 00:25:38 -0400 Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 727702A951; Mon, 13 Jun 2022 21:25:37 -0700 (PDT) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 36DCC1A2682; Tue, 14 Jun 2022 06:25:36 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E0B631A2685; Tue, 14 Jun 2022 06:25:35 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 05267180222C; Tue, 14 Jun 2022 12:25:33 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] ASoC: dt-bindings: fsl-sai: Add new property to configure dataline Date: Tue, 14 Jun 2022 12:11:23 +0800 Message-Id: <1655179884-12278-7-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" "fsl,dataline" is added to configure the dataline of SAI. It has 3 value for each configuration, first one means the type: I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is dataline mask for 'tx'. for example: fsl,dataline =3D <1 0xff 0xff 2 0xff 0x11>, it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). Signed-off-by: Shengjiu Wang --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Document= ation/devicetree/bindings/sound/fsl-sai.txt index c71c5861d787..4c66e6a1a533 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -49,6 +49,14 @@ Required properties: receive data by following their own bit clocks and frame sync clocks separately. =20 + - fsl,dataline : configure the dataline. it has 3 value for each = configuration + first one means the type: I2S(1) or PDM(2) + second one is dataline mask for 'rx' + third one is dataline mask for 'tx'. + for example: fsl,dataline =3D <1 0xff 0xff 2 0xf= f 0x11>; + it means I2S type rx mask is 0xff, tx mask is 0x= ff, PDM type + rx mask is 0xff, tx mask is 0x11 (dataline 1 and= 4 enabled). + Optional properties: =20 - big-endian : Boolean property, required if all the SAI --=20 2.17.1 From nobody Wed Apr 29 08:09:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 925E8C433EF for ; Tue, 14 Jun 2022 04:26:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351759AbiFNE0S (ORCPT ); Tue, 14 Jun 2022 00:26:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350710AbiFNEZk (ORCPT ); Tue, 14 Jun 2022 00:25:40 -0400 Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFAAF2AC66; Mon, 13 Jun 2022 21:25:38 -0700 (PDT) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A127220271B; Tue, 14 Jun 2022 06:25:37 +0200 (CEST) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 1A704202718; Tue, 14 Jun 2022 06:25:37 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 33D9B180219B; Tue, 14 Jun 2022 12:25:35 +0800 (+08) From: Shengjiu Wang To: nicoleotsuka@gmail.com, Xiubo.Lee@gmail.com, festevam@gmail.com, shengjiu.wang@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.com, alsa-devel@alsa-project.org, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] ASoC: fsl_sai: Configure dataline/FIFO information from dts property Date: Tue, 14 Jun 2022 12:11:24 +0800 Message-Id: <1655179884-12278-8-git-send-email-shengjiu.wang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> References: <1655179884-12278-1-git-send-email-shengjiu.wang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SAI has multiple successive FIFO registers, but in some use case the required dataline/FIFOs are not successive, so need get such information from dts property "fsl,dataline" fsl,dataline has 3 values for each configuration: first one means the type: I2S(1) or DSD(2), second one is dataline mask for 'rx', third one is dataline mask for 'tx'. Also set dma peripheral address and TRCE bits according to data lane. Signed-off-by: Shengjiu Wang Signed-off-by: Viorel Suman --- sound/soc/fsl/fsl_sai.c | 161 +++++++++++++++++++++++++++++++++++++++- sound/soc/fsl/fsl_sai.h | 17 +++++ 2 files changed, 174 insertions(+), 4 deletions(-) diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index 86aa0baba848..f5eabb0b10e8 100644 --- a/sound/soc/fsl/fsl_sai.c +++ b/sound/soc/fsl/fsl_sai.c @@ -487,13 +487,18 @@ static int fsl_sai_hw_params(struct snd_pcm_substream= *substream, unsigned int ofs =3D sai->soc_data->reg_offset; bool tx =3D substream->stream =3D=3D SNDRV_PCM_STREAM_PLAYBACK; unsigned int channels =3D params_channels(params); + struct snd_dmaengine_dai_dma_data *dma_params; + struct fsl_sai_dl_cfg *dl_cfg =3D sai->dl_cfg; u32 word_width =3D params_width(params); + int trce_mask =3D 0, dl_cfg_idx =3D 0; + int dl_cfg_cnt =3D sai->dl_cfg_cnt; + u32 dl_type =3D FSL_SAI_DL_I2S; u32 val_cr4 =3D 0, val_cr5 =3D 0; u32 slots =3D (channels =3D=3D 1) ? 2 : channels; u32 slot_width =3D word_width; int adir =3D tx ? RX : TX; u32 pins, bclk; - int ret; + int ret, i; =20 if (sai->slots) slots =3D sai->slots; @@ -507,8 +512,22 @@ static int fsl_sai_hw_params(struct snd_pcm_substream = *substream, * PDM mode, channels are independent * each channels are on one dataline/FIFO. */ - if (sai->is_pdm_mode) + if (sai->is_pdm_mode) { pins =3D channels; + dl_type =3D FSL_SAI_DL_PDM; + } + + for (i =3D 0; i < dl_cfg_cnt; i++) { + if (dl_cfg[i].type =3D=3D dl_type && dl_cfg[i].pins[tx] =3D=3D pins) { + dl_cfg_idx =3D i; + break; + } + } + + if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) < pins) { + dev_err(cpu_dai->dev, "channel not supported\n"); + return -EINVAL; + } =20 bclk =3D params_rate(params) * (sai->bclk_ratio ? sai->bclk_ratio : slots= * slot_width); =20 @@ -571,13 +590,28 @@ static int fsl_sai_hw_params(struct snd_pcm_substream= *substream, FSL_SAI_CR5_FBT_MASK, val_cr5); } =20 - if (sai->soc_data->pins > 1) + if (hweight8(dl_cfg[dl_cfg_idx].mask[tx]) <=3D 1) + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), + FSL_SAI_CR4_FCOMB_MASK, 0); + else regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_FCOMB_MASK, FSL_SAI_CR4_FCOMB_SOFT); =20 + dma_params =3D tx ? &sai->dma_params_tx : &sai->dma_params_rx; + dma_params->addr =3D sai->res->start + FSL_SAI_xDR0(tx) + + dl_cfg[dl_cfg_idx].start_off[tx] * 0x4; + + /* Find a proper tcre setting */ + for (i =3D 0; i < sai->soc_data->pins; i++) { + trce_mask =3D (1 << (i + 1)) - 1; + if (hweight8(dl_cfg[dl_cfg_idx].mask[tx] & trce_mask) =3D=3D pins) + break; + } + regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs), FSL_SAI_CR3_TRCE_MASK, - FSL_SAI_CR3_TRCE((1 << pins) - 1)); + FSL_SAI_CR3_TRCE((dl_cfg[dl_cfg_idx].mask[tx] & trce_mask))); + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs), FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK | FSL_SAI_CR4_CHMOD_MASK, @@ -1068,6 +1102,118 @@ static int fsl_sai_check_version(struct device *dev) return 0; } =20 +/* + * Calculate the offset between first two datalines, don't + * different offset in one case. + */ +static unsigned int fsl_sai_calc_dl_off(unsigned long dl_mask) +{ + int fbidx, nbidx, offset; + + fbidx =3D find_first_bit(&dl_mask, FSL_SAI_DL_NUM); + nbidx =3D find_next_bit(&dl_mask, FSL_SAI_DL_NUM, fbidx + 1); + offset =3D nbidx - fbidx - 1; + + return (offset < 0 || offset >=3D (FSL_SAI_DL_NUM - 1) ? 0 : offset); +} + +/* + * read the fsl,dataline property from dts file. + * It has 3 value for each configuration, first one means the type: + * I2S(1) or PDM(2), second one is dataline mask for 'rx', third one is + * dataline mask for 'tx'. for example + * + * fsl,dataline =3D <1 0xff 0xff 2 0xff 0x11>, + * + * It means I2S type rx mask is 0xff, tx mask is 0xff, PDM type + * rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled). + * + */ +static int fsl_sai_read_dlcfg(struct fsl_sai *sai) +{ + struct platform_device *pdev =3D sai->pdev; + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret, elems, i, index, num_cfg; + char *propname =3D "fsl,dataline"; + struct fsl_sai_dl_cfg *cfg; + unsigned long dl_mask; + unsigned int soc_dl; + u32 rx, tx, type; + + elems =3D of_property_count_u32_elems(np, propname); + + if (elems <=3D 0) { + elems =3D 0; + } else if (elems % 3) { + dev_err(dev, "Number of elements must be divisible to 3.\n"); + return -EINVAL; + } + + num_cfg =3D elems / 3; + /* Add one more for default value */ + cfg =3D devm_kzalloc(&pdev->dev, (num_cfg + 1) * sizeof(*cfg), GFP_KERNEL= ); + if (!cfg) + return -ENOMEM; + + /* Consider default value "0 0xFF 0xFF" if property is missing */ + soc_dl =3D BIT(sai->soc_data->pins) - 1; + cfg[0].type =3D FSL_SAI_DL_DEFAULT; + cfg[0].pins[0] =3D sai->soc_data->pins; + cfg[0].mask[0] =3D soc_dl; + cfg[0].start_off[0] =3D 0; + cfg[0].next_off[0] =3D 0; + + cfg[0].pins[1] =3D sai->soc_data->pins; + cfg[0].mask[1] =3D soc_dl; + cfg[0].start_off[1] =3D 0; + cfg[0].next_off[1] =3D 0; + for (i =3D 1, index =3D 0; i < num_cfg + 1; i++) { + /* + * type of dataline + * 0 means default mode + * 1 means I2S mode + * 2 means PDM mode + */ + ret =3D of_property_read_u32_index(np, propname, index++, &type); + if (ret) + return -EINVAL; + + ret =3D of_property_read_u32_index(np, propname, index++, &rx); + if (ret) + return -EINVAL; + + ret =3D of_property_read_u32_index(np, propname, index++, &tx); + if (ret) + return -EINVAL; + + if ((rx & ~soc_dl) || (tx & ~soc_dl)) { + dev_err(dev, "dataline cfg[%d] setting error, mask is 0x%x\n", i, soc_d= l); + return -EINVAL; + } + + rx =3D rx & soc_dl; + tx =3D tx & soc_dl; + + cfg[i].type =3D type; + cfg[i].pins[0] =3D hweight8(rx); + cfg[i].mask[0] =3D rx; + dl_mask =3D rx; + cfg[i].start_off[0] =3D find_first_bit(&dl_mask, FSL_SAI_DL_NUM); + cfg[i].next_off[0] =3D fsl_sai_calc_dl_off(rx); + + cfg[i].pins[1] =3D hweight8(tx); + cfg[i].mask[1] =3D tx; + dl_mask =3D tx; + cfg[i].start_off[1] =3D find_first_bit(&dl_mask, FSL_SAI_DL_NUM); + cfg[i].next_off[1] =3D fsl_sai_calc_dl_off(tx); + } + + sai->dl_cfg =3D cfg; + sai->dl_cfg_cnt =3D num_cfg + 1; + return 0; +} + static int fsl_sai_runtime_suspend(struct device *dev); static int fsl_sai_runtime_resume(struct device *dev); =20 @@ -1134,6 +1280,13 @@ static int fsl_sai_probe(struct platform_device *pde= v) else sai->mclk_clk[0] =3D sai->bus_clk; =20 + /* read dataline mask for rx and tx*/ + ret =3D fsl_sai_read_dlcfg(sai); + if (ret < 0) { + dev_err(dev, "failed to read dlcfg %d\n", ret); + return ret; + } + irq =3D platform_get_irq(pdev, 0); if (irq < 0) return irq; diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h index 4d657edc9c9f..9bb8ced520c8 100644 --- a/sound/soc/fsl/fsl_sai.h +++ b/sound/soc/fsl/fsl_sai.h @@ -218,6 +218,13 @@ =20 #define PMQOS_CPU_LATENCY BIT(0) =20 +/* Max number of dataline */ +#define FSL_SAI_DL_NUM (8) +/* default dataline type is zero */ +#define FSL_SAI_DL_DEFAULT (0) +#define FSL_SAI_DL_I2S BIT(0) +#define FSL_SAI_DL_PDM BIT(1) + struct fsl_sai_soc_data { bool use_imx_pcm; bool use_edma; @@ -253,6 +260,14 @@ struct fsl_sai_param { u32 dataline; }; =20 +struct fsl_sai_dl_cfg { + unsigned int type; + unsigned int pins[2]; + unsigned int mask[2]; + unsigned int start_off[2]; + unsigned int next_off[2]; +}; + struct fsl_sai { struct platform_device *pdev; struct regmap *regmap; @@ -265,6 +280,8 @@ struct fsl_sai { bool is_dsp_mode; bool is_pdm_mode; bool synchronous[2]; + struct fsl_sai_dl_cfg *dl_cfg; + unsigned int dl_cfg_cnt; =20 unsigned int mclk_id[2]; unsigned int mclk_streams; --=20 2.17.1