From nobody Tue Apr 28 01:11:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0212C433EF for ; Wed, 8 Jun 2022 19:32:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231328AbiFHTcp (ORCPT ); Wed, 8 Jun 2022 15:32:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231705AbiFHTcm (ORCPT ); Wed, 8 Jun 2022 15:32:42 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EBF61E7372; Wed, 8 Jun 2022 12:32:40 -0700 (PDT) Date: Wed, 08 Jun 2022 19:32:37 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1654716758; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=71uqOL5+ANg3vD/7eysxY3A9V563Mf1GUNlN1il7T3g=; b=tWlhmKVLlEK5ifogRMjwC7kFhmGfInRqCSm6CZkcAzkvsItTJrlaOsuKZ8gRMzAUCcTKjR J16WC7byVgAsonWcpcgZiRIQQbNU3SGHmYG12iYghUpjRUJzF96V9MIrjstAdzRKUTy9ge izjY8D3YIi3eg2dLOqOckM6riRvtKml1irl76Ahr38bZ+PeGXlbOZRdYBjLSsfrAHCgSHf V6VOxw4tGqxgRy77FCP8kVIaXfDR2yae56KRPhxXnO2dZ7PyiEJ0VJyRJUP3aIqEF23B8a fYjFFef2Y2FQFB7D1ZuAEuCdkdeUb4cx463cbof5R+JmZgIYZRt343Fwg3GJwA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1654716758; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=71uqOL5+ANg3vD/7eysxY3A9V563Mf1GUNlN1il7T3g=; b=Iilf7K/1BjiCSNbIrbLsI5esS+vkJHTzaCP4EzDcrSolqnlKOBlRE8hagfVd/SKd7yOaG1 WNh+H05uX31xJABw== From: "tip-bot2 for Chang S. Bae" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/fpu] intel_idle: Add a new flag to initialize the AMX state Cc: Zhang Rui , "Peter Zijlstra (Intel)" , "Chang S. Bae" , Dave Hansen , "Rafael J. Wysocki" , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220608164748.11864-3-chang.seok.bae@intel.com> References: <20220608164748.11864-3-chang.seok.bae@intel.com> MIME-Version: 1.0 Message-ID: <165471675715.4207.17983340888752028780.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/fpu branch of tip: Commit-ID: 43843d58393026fef4a43d192b641a4fabdc42bf Gitweb: https://git.kernel.org/tip/43843d58393026fef4a43d192b641a4fa= bdc42bf Author: Chang S. Bae AuthorDate: Wed, 08 Jun 2022 09:47:48 -07:00 Committer: Dave Hansen CommitterDate: Wed, 08 Jun 2022 12:04:11 -07:00 intel_idle: Add a new flag to initialize the AMX state The non-initialized AMX state can be the cause of C-state demotion from C6 to C1E. This low-power idle state may improve power savings and thus result in a higher available turbo frequency budget. This behavior is implementation-specific. Initialize the state for the C6 entrance of Sapphire Rapids as needed. Tested-by : Zhang Rui Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Chang S. Bae Signed-off-by: Dave Hansen Acked-by: Rafael J. Wysocki Link: https://lkml.kernel.org/r/20220608164748.11864-3-chang.seok.bae@intel= .com Tested-by : Zhang Rui --- drivers/idle/intel_idle.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index b7640cf..d357908 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c @@ -54,6 +54,7 @@ #include #include #include +#include =20 #define INTEL_IDLE_VERSION "0.5.1" =20 @@ -101,6 +102,11 @@ static unsigned int mwait_substates __initdata; #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15) =20 /* + * Initialize large xstate for the C6-state entrance. + */ +#define CPUIDLE_FLAG_INIT_XSTATE BIT(16) + +/* * MWAIT takes an 8-bit "hint" in EAX "suggesting" * the C-state (top nibble) and sub-state (bottom nibble) * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc. @@ -134,6 +140,9 @@ static __cpuidle int intel_idle(struct cpuidle_device *= dev, if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE) local_irq_enable(); =20 + if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) + fpu_idle_fpregs(); + mwait_idle_with_hints(eax, ecx); =20 return index; @@ -154,8 +163,12 @@ static __cpuidle int intel_idle(struct cpuidle_device = *dev, static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) { - unsigned long eax =3D flg2MWAIT(drv->states[index].flags); unsigned long ecx =3D 1; /* break on interrupt flag */ + struct cpuidle_state *state =3D &drv->states[index]; + unsigned long eax =3D flg2MWAIT(state->flags); + + if (state->flags & CPUIDLE_FLAG_INIT_XSTATE) + fpu_idle_fpregs(); =20 mwait_idle_with_hints(eax, ecx); =20 @@ -790,7 +803,8 @@ static struct cpuidle_state spr_cstates[] __initdata = =3D { { .name =3D "C6", .desc =3D "MWAIT 0x20", - .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, + .flags =3D MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED | + CPUIDLE_FLAG_INIT_XSTATE, .exit_latency =3D 290, .target_residency =3D 800, .enter =3D &intel_idle,