From nobody Tue Apr 28 02:37:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5A36CCA47F for ; Tue, 7 Jun 2022 12:36:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243851AbiFGMgR (ORCPT ); Tue, 7 Jun 2022 08:36:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243823AbiFGMgH (ORCPT ); Tue, 7 Jun 2022 08:36:07 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1600CC5D9E; Tue, 7 Jun 2022 05:36:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1654605366; x=1686141366; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=TRO3yMYxgaq8AuJJz5Yh1/P8fYb+bn8NnBoj5lR68G4=; b=akyPJRvYqLRyiYztfC6EJXTJ0otkExPt0oTplXdQtlgbeSOQ8bucDf5/ zvM05jOrwel8ztNKVOBWTliyeZqx+lq/canmXZ02v+L2OUZr0J56uRpiL Has/ZAAn1+Q8JZ0W23A+ZQeZR3OVSUFCDUVxM0I1hm4tP8+VZhaAMqZm3 M=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 07 Jun 2022 05:36:05 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 05:36:05 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 05:36:04 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 05:35:58 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH 1/2] soundwire: qcom: Add flag for software clock gating check Date: Tue, 7 Jun 2022 18:05:33 +0530 Message-ID: <1654605334-32030-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1654605334-32030-1-git-send-email-quic_srivasam@quicinc.com> References: <1654605334-32030-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add flag in qcom_swrm_data private data structure for validating software colck gating control requirement. Signed-off-by: Srinivasa Rao Mandadapu --- drivers/soundwire/qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index a3fccf0..38c3bf5 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -181,6 +181,7 @@ struct qcom_swrm_ctrl { struct qcom_swrm_data { u32 default_cols; u32 default_rows; + bool sw_clk_gate_required; }; =20 static const struct qcom_swrm_data swrm_v1_3_data =3D { --=20 2.7.4 From nobody Tue Apr 28 02:37:19 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5466C43334 for ; Tue, 7 Jun 2022 12:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243870AbiFGMgZ (ORCPT ); Tue, 7 Jun 2022 08:36:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243856AbiFGMgO (ORCPT ); Tue, 7 Jun 2022 08:36:14 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26671C4EB9; Tue, 7 Jun 2022 05:36:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1654605372; x=1686141372; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=fYpPCX6VZdvNlaz5PU1EmmzGezp4ojXcHXRAL2naybc=; b=WAdtr08VdHF0FaoCNYSI3IjbIWdRE0OWKShlPAGcCv6s9+LD0IOTMQGe /WHZTnK/nb4EjByDLNHFQ8HhHRFLvtEwKVswmKdw80OTqSIjEXobgrC9f a/Yk4LGkurTYgvGK7OjYIPjbT4TYADnq8AbFqxu6v2a2XlerKWuJnoR7h s=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 07 Jun 2022 05:36:12 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 05:36:11 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 05:36:10 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 7 Jun 2022 05:36:04 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , , , , , , , , CC: Srinivasa Rao Mandadapu Subject: [PATCH 2/2] ASoC: qcom: soundwire: Add software clock gating requirement check Date: Tue, 7 Jun 2022 18:05:34 +0530 Message-ID: <1654605334-32030-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1654605334-32030-1-git-send-email-quic_srivasam@quicinc.com> References: <1654605334-32030-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Validate software clock gating required or not and do software clock gating on hclk if soundwire is operational and keep it running by adding flag in private dat structure. This is to avoid conflict between older architectures, where software clock gating is not required and on latest architectues, where software clock gating is mandatory. Signed-off-by: Srinivasa Rao Mandadapu Reported-by: kernel test robot --- drivers/soundwire/qcom.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c index 38c3bf5..4896e92 100644 --- a/drivers/soundwire/qcom.c +++ b/drivers/soundwire/qcom.c @@ -194,6 +194,12 @@ static const struct qcom_swrm_data swrm_v1_5_data =3D { .default_cols =3D 16, }; =20 +static const struct qcom_swrm_data swrm_v1_6_data =3D { + .default_rows =3D 50, + .default_cols =3D 16, + .sw_clk_gate_required =3D 1, +}; + #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus) =20 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg, @@ -659,7 +665,8 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl) val =3D FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_ind= ex); val |=3D FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_in= dex); =20 - reset_control_reset(ctrl->audio_cgcr); + if (data->sw_clk_gate_required) + reset_control_reset(ctrl->audio_cgcr); =20 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); =20 @@ -1312,6 +1319,15 @@ static int qcom_swrm_probe(struct platform_device *p= dev) return PTR_ERR(ctrl->mmio); } =20 + if (data->sw_clk_gate_required) { + ctrl->audio_cgcr =3D devm_reset_control_get_exclusive(dev, "swr_audio_cg= cr"); + if (IS_ERR(ctrl->audio_cgcr)) { + dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n"); + ret =3D PTR_ERR(ctrl->audio_cgcr); + goto err_init; + } + } + ctrl->irq =3D of_irq_get(dev->of_node, 0); if (ctrl->irq < 0) { ret =3D ctrl->irq; @@ -1337,10 +1353,6 @@ static int qcom_swrm_probe(struct platform_device *p= dev) ctrl->bus.compute_params =3D &qcom_swrm_compute_params; ctrl->bus.clk_stop_timeout =3D 300; =20 - ctrl->audio_cgcr =3D devm_reset_control_get_exclusive(dev, "swr_audio_cgc= r"); - if (IS_ERR(ctrl->audio_cgcr)) - dev_err(dev, "Failed to get audio_cgcr reset required for soundwire-v1.6= .0\n"); - ret =3D qcom_swrm_get_port_config(ctrl); if (ret) goto err_clk; @@ -1494,7 +1506,8 @@ static int __maybe_unused swrm_runtime_resume(struct = device *dev) qcom_swrm_get_device_status(ctrl); sdw_handle_slave_status(&ctrl->bus, ctrl->status); } else { - reset_control_reset(ctrl->audio_cgcr); + if (data->sw_clk_gate_required) + reset_control_reset(ctrl->audio_cgcr); =20 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, @@ -1559,7 +1572,7 @@ static const struct dev_pm_ops swrm_dev_pm_ops =3D { static const struct of_device_id qcom_swrm_of_match[] =3D { { .compatible =3D "qcom,soundwire-v1.3.0", .data =3D &swrm_v1_3_data }, { .compatible =3D "qcom,soundwire-v1.5.1", .data =3D &swrm_v1_5_data }, - { .compatible =3D "qcom,soundwire-v1.6.0", .data =3D &swrm_v1_5_data }, + { .compatible =3D "qcom,soundwire-v1.6.0", .data =3D &swrm_v1_6_data }, {/* sentinel */}, }; =20 --=20 2.7.4