From nobody Tue Apr 28 18:21:09 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B70DC433EF for ; Tue, 31 May 2022 07:35:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244528AbiEaHfW (ORCPT ); Tue, 31 May 2022 03:35:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244517AbiEaHfF (ORCPT ); Tue, 31 May 2022 03:35:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5820D82172; Tue, 31 May 2022 00:34:53 -0700 (PDT) Date: Tue, 31 May 2022 07:34:49 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1653982490; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MKjc1ott4nliLMZ5rP684FS2s1uy73yIZ5lLMoWVCvI=; b=t1Zijdb8tKvNB72tlH87nB54Uwy7Ez6EXpzsN+hBll1eLkHsp03lZ3YhfWPmyThZzoBRy2 FjrGF4mgUelUyX/MYvDWBIZYDpzKiS1VtwQz2LgMwBSsfy+Yn4PxoPnO9YHYYtnWuaNswH xf9IwScrEROgKKJxzC+BIqNxGn3ROkhYzon4ReSMLzgY0ybxoWv9GeMLMW8X57E3lfMdME 6THkwrOb9LICgbd5SfFvpjXZ5U3nDzIfKs1JwisUDUQKF3PMZ2j9DP9/pjQJ+bB/a1Yt9T 5j1ayVTsUThdkqjpXjYPj7y1jUMupATHK/LHJ3Cmq6fv5AYPulWD0ik0vrYymQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1653982490; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MKjc1ott4nliLMZ5rP684FS2s1uy73yIZ5lLMoWVCvI=; b=oCYFR/ninVASyT0KNBW+FDlWHmYA/VXNFIxP/r4NBvZHqyUefPwkIXcr+cgGFTwqcIFika mnpSYesbrCXqeZCg== From: "tip-bot2 for Borislav Petkov" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/microcode] x86/microcode: Default-disable late loading Cc: Borislav Petkov , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220525161232.14924-3-bp@alien8.de> References: <20220525161232.14924-3-bp@alien8.de> MIME-Version: 1.0 Message-ID: <165398248963.4207.4617963203135266046.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/microcode branch of tip: Commit-ID: a77a94f86273ce42a39cb479217dd8d68acfe0ff Gitweb: https://git.kernel.org/tip/a77a94f86273ce42a39cb479217dd8d68= acfe0ff Author: Borislav Petkov AuthorDate: Wed, 25 May 2022 18:12:30 +02:00 Committer: Thomas Gleixner CommitterDate: Tue, 31 May 2022 09:31:19 +02:00 x86/microcode: Default-disable late loading It is dangerous and it should not be used anyway - there's a nice early loading already. Requested-by: Peter Zijlstra (Intel) Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20220525161232.14924-3-bp@alien8.de --- arch/x86/Kconfig | 11 +++++++++++ arch/x86/kernel/cpu/common.c | 2 ++ arch/x86/kernel/cpu/microcode/core.c | 7 ++++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f423a2d..976309d 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1350,6 +1350,17 @@ config MICROCODE_AMD If you select this option, microcode patch loading support for AMD processors will be enabled. =20 +config MICROCODE_LATE_LOADING + bool "Late microcode loading (DANGEROUS)" + default n + depends on MICROCODE + help + Loading microcode late, when the system is up and executing instructions + is a tricky business and should be avoided if possible. Just the sequen= ce + of synchronizing all cores and SMT threads is one fragile dance which d= oes + not guarantee that cores might not softlock after the loading. Therefor= e, + use this at your own risk. Late loading taints the kernel too. + config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" help diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2e91427..c296cb1 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2222,6 +2222,7 @@ void cpu_init_secondary(void) } #endif =20 +#ifdef CONFIG_MICROCODE_LATE_LOADING /* * The microcode loader calls this upon late microcode load to recheck fea= tures, * only when microcode has been updated. Caller holds microcode_mutex and = CPU @@ -2251,6 +2252,7 @@ void microcode_check(void) pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); pr_warn("x86/CPU: Please consider either early loading through initrd/bui= lt-in or a potential BIOS update.\n"); } +#endif =20 /* * Invoked from core CPU hotplug code after hotplug operations diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index b72c413..c717db6 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -376,6 +376,7 @@ static int apply_microcode_on_target(int cpu) /* fake device for request_firmware */ static struct platform_device *microcode_pdev; =20 +#ifdef CONFIG_MICROCODE_LATE_LOADING /* * Late loading dance. Why the heavy-handed stomp_machine effort? * @@ -543,6 +544,9 @@ put: return ret; } =20 +static DEVICE_ATTR_WO(reload); +#endif + static ssize_t version_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -559,7 +563,6 @@ static ssize_t pf_show(struct device *dev, return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); } =20 -static DEVICE_ATTR_WO(reload); static DEVICE_ATTR(version, 0444, version_show, NULL); static DEVICE_ATTR(processor_flags, 0444, pf_show, NULL); =20 @@ -712,7 +715,9 @@ static int mc_cpu_down_prep(unsigned int cpu) } =20 static struct attribute *cpu_root_microcode_attrs[] =3D { +#ifdef CONFIG_MICROCODE_LATE_LOADING &dev_attr_reload.attr, +#endif NULL };