From nobody Fri May 8 06:01:29 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9B17C433EF for ; Tue, 10 May 2022 09:11:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238481AbiEJJPl (ORCPT ); Tue, 10 May 2022 05:15:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238438AbiEJJPi (ORCPT ); Tue, 10 May 2022 05:15:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0BA33F893; Tue, 10 May 2022 02:11:40 -0700 (PDT) Date: Tue, 10 May 2022 09:11:38 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1652173899; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DcKTZBkAjH+M8b8GOnVitX035y0f1C6mlMpXMdWwxn8=; b=ES79iSC7jF2rEurIExXvNiJ8ypjoHg4JPo/97v9Ks58pl9UJxAwaqTk65NFnc51QIAdbJ6 tzz7lVyJ4ZG4UP2WkYPLXtsjRdBMClSTPjuKFkMwEo3h1S2c9MynrCJxqw5QZQu8x1WdZe htIXyqobQS736lbfDGbaSvbIlZ8bC4ExDxt36g+CRVcVgPfStdEwfg7Plas3u0llt81pRS I4w/3EJJwEQN0vXdx3SPXzpiw+3rQ9vegYsVdx8NvyHqJQnB2dqY3I76v4lmzTxTtnB4rJ fWMJB3u+16IlGaY2T/k9u+noQscZWSRr9TTfmTB1abLGyj91du1HGlqUzfIjLQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1652173899; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DcKTZBkAjH+M8b8GOnVitX035y0f1C6mlMpXMdWwxn8=; b=Rb3BbD+I/FlnN6+mVj2HMen8LSthBkmn5pA+PSM/dQhX+nRvEPnfjwrxsBY4jlOM0n71QR Ii8I1B4cW2VaW3Bw== From: "tip-bot2 for Ravi Bangoria" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/amd/ibs: Use interrupt regs ip for stack unwinding Cc: Dmitry Monakhov , Peter Zijlstra , Ravi Bangoria , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220429051441.14251-1-ravi.bangoria@amd.com> References: <20220429051441.14251-1-ravi.bangoria@amd.com> MIME-Version: 1.0 Message-ID: <165217389810.4207.18154014906972334877.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 3d47083b9ff46863e8374ad3bb5edb5e464c75f8 Gitweb: https://git.kernel.org/tip/3d47083b9ff46863e8374ad3bb5edb5e4= 64c75f8 Author: Ravi Bangoria AuthorDate: Fri, 29 Apr 2022 10:44:41 +05:30 Committer: Peter Zijlstra CommitterDate: Tue, 10 May 2022 11:00:45 +02:00 perf/amd/ibs: Use interrupt regs ip for stack unwinding IbsOpRip is recorded when IBS interrupt is triggered. But there is a skid from the time IBS interrupt gets triggered to the time the interrupt is presented to the core. Meanwhile processor would have moved ahead and thus IbsOpRip will be inconsistent with rsp and rbp recorded as part of the interrupt regs. This causes issues while unwinding stack using the ORC unwinder as it needs consistent rip, rsp and rbp. Fix this by using rip from interrupt regs instead of IbsOpRip for stack unwinding. Fixes: ee9f8fce99640 ("x86/unwind: Add the ORC unwinder") Reported-by: Dmitry Monakhov Suggested-by: Peter Zijlstra Signed-off-by: Ravi Bangoria Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20220429051441.14251-1-ravi.bangoria@amd.com --- arch/x86/events/amd/ibs.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 9739019..11e8b49 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -304,6 +304,16 @@ static int perf_ibs_init(struct perf_event *event) hwc->config_base =3D perf_ibs->msr; hwc->config =3D config; =20 + /* + * rip recorded by IbsOpRip will not be consistent with rsp and rbp + * recorded as part of interrupt regs. Thus we need to use rip from + * interrupt regs while unwinding call stack. Setting _EARLY flag + * makes sure we unwind call-stack before perf sample rip is set to + * IbsOpRip. + */ + if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) + event->attr.sample_type |=3D __PERF_SAMPLE_CALLCHAIN_EARLY; + return 0; } =20 @@ -687,6 +697,14 @@ fail: data.raw =3D &raw; } =20 + /* + * rip recorded by IbsOpRip will not be consistent with rsp and rbp + * recorded as part of interrupt regs. Thus we need to use rip from + * interrupt regs while unwinding call stack. + */ + if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN) + data.callchain =3D perf_callchain(event, iregs); + throttle =3D perf_event_overflow(event, &data, ®s); out: if (throttle) {