From nobody Sun May 10 10:34:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D9CC433EF for ; Thu, 5 May 2022 15:05:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381054AbiEEPIm (ORCPT ); Thu, 5 May 2022 11:08:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381041AbiEEPIj (ORCPT ); Thu, 5 May 2022 11:08:39 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43FE35AEDE; Thu, 5 May 2022 08:04:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651763099; x=1683299099; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=lFrc9vNgpG72NB/i42cRRORkDY6B9Q0EJvCBYSEohME=; b=YGYmikUqo3uj2/HZ6sWnZh84opwyhptfmRja0TDuE7e92m4GGY2OY2f2 0Z1VJZWOyW0liv+6GsM+IBtgA3ubv+XvwXIu1q2xryWO/lMdyU0EEht/i DvMQEQu2JxHAujcDSJImsVJt2A6yCzkdpw8Zv9KEAtq+PgypRktEEdIni s=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 May 2022 08:04:59 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 08:04:58 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:04:58 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:04:53 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v14 1/4] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Thu, 5 May 2022 20:33:21 +0530 Message-ID: <1651763004-32533-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> References: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinmux nodes for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++= ++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 6a14259..754da58 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -367,6 +367,20 @@ bias-disable; }; =20 +&mi2s1_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength =3D <6>; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins =3D "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index ccf5e95..c5b6b46 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3890,6 +3890,46 @@ function =3D "edp_hot"; }; =20 + mi2s0_data0: mi2s0-data0 { + pins =3D "gpio98"; + function =3D "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins =3D "gpio99"; + function =3D "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins =3D "gpio96"; + function =3D "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins =3D "gpio97"; + function =3D "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins =3D "gpio100"; + function =3D "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins =3D "gpio107"; + function =3D "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins =3D "gpio106"; + function =3D "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins =3D "gpio108"; + function =3D "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; --=20 2.7.4 From nobody Sun May 10 10:34:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D375C4332F for ; Thu, 5 May 2022 15:05:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381063AbiEEPIz (ORCPT ); Thu, 5 May 2022 11:08:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381041AbiEEPIq (ORCPT ); Thu, 5 May 2022 11:08:46 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 090465BD08; Thu, 5 May 2022 08:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651763104; x=1683299104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=aB58FSCNvlypPbXyoLFcv4iQe6BnMf6/0pbdDWGqfrY=; b=TGq5asME8Qp/PfVe/fzdzH1+FOufXA3rI5qBUekeq1Z8grW8IW272000 UJzuVcgQwoQzJC5A+Xi1vmYijOfFdMtqwiMn4kAF9YUxoE5nPwxBudv5U cW1npmL+pY0Bj6i1Y5mwh2Hzv8GrGQ6po0F6kGtmg2fSDiJyrC9roNWRU k=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 May 2022 08:05:03 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 08:05:03 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:05:02 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:04:58 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v14 2/4] arm64: dts: qcom: sc7280: Add secondary MI2S pinmux specifications for CRD 3.0/3.1 Date: Thu, 5 May 2022 20:33:22 +0530 Message-ID: <1651763004-32533-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> References: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add drive strength property for secondary MI2S on sc7280 based platforms of rev5+ (aka CRD 3.0/3.1) boards. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64= /boot/dts/qcom/sc7280-herobrine-crd.dts index b06f61e..deaea3a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -111,6 +111,20 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is not hooked up on Qcard, it gets no name. */ =20 +&mi2s1_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength =3D <6>; +}; + &pm8350c_gpios { gpio-line-names =3D "FLASH_STROBE_1", /* 1 */ "AP_SUSPEND", --=20 2.7.4 From nobody Sun May 10 10:34:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA2D2C433EF for ; Thu, 5 May 2022 15:05:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345583AbiEEPJg (ORCPT ); Thu, 5 May 2022 11:09:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381079AbiEEPIu (ORCPT ); Thu, 5 May 2022 11:08:50 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB3125BD1D; Thu, 5 May 2022 08:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651763109; x=1683299109; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Crp0/VjQyGgg2AdVT03Mtv9ivsHAVt3ffB47msXO63w=; b=TFD2zYqoB/u/HxvXOBWnxtb0wPKVVPFFJ/MCSoO9evKoZoHQu/b3L5oB iXsao7exH+7PQm+inYKuIKxx+loly4dVW0e5R3+lf85B0cGDhoIucFona zk4QLgvYlMQWXKWsTPTJLeSc307DpTVIXOHE4A4k7jBDywSJ9UPYrlpH7 k=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 05 May 2022 08:05:08 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 May 2022 08:05:07 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:05:06 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:05:02 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v14 3/4] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Date: Thu, 5 May 2022 20:33:23 +0530 Message-ID: <1651763004-32533-4-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> References: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LPASS LPI pinctrl node required for Audio functionality on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 62 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 91 ++++++++++++++++++++++++++++= ++++ 2 files changed, 153 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 754da58..a28e899 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -367,6 +367,68 @@ bias-disable; }; =20 +&lpass_dmic01_clk { + drive-strength =3D <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength =3D <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength =3D <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength =3D <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; +}; + &mi2s1_data0 { drive-strength =3D <6>; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index c5b6b46..89b16e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2224,6 +2224,97 @@ qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sc7280-lpass-lpi-pinctrl"; + reg =3D <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + #clock-cells =3D <1>; + + lpass_dmic01_clk: dmic01-clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + lpass_dmic01_clk_sleep: dmic01-clk-sleep { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + lpass_dmic01_data: dmic01-data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + + lpass_dmic01_data_sleep: dmic01-data-sleep { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + + lpass_dmic23_clk: dmic23-clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + lpass_dmic23_clk_sleep: dmic23-clk-sleep { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + lpass_dmic23_data: dmic23-data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + + lpass_dmic23_data_sleep: dmic23-data-sleep { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + + lpass_rx_swr_clk: rx-swr-clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + lpass_rx_swr_clk_sleep: rx-swr-clk-sleep { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + lpass_rx_swr_data: rx-swr-data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + + lpass_rx_swr_data_sleep: rx-swr-data-sleep { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + + lpass_tx_swr_clk: tx-swr-clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + lpass_tx_swr_clk_sleep: tx-swr-clk-sleep { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + lpass_tx_swr_data: tx-swr-data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + + lpass_tx_swr_data_sleep: tx-swr-data-sleep { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + }; + gpu: gpu@3d00000 { compatible =3D "qcom,adreno-635.0", "qcom,adreno"; reg =3D <0 0x03d00000 0 0x40000>, --=20 2.7.4 From nobody Sun May 10 10:34:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AC24C433F5 for ; Thu, 5 May 2022 15:06:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1381096AbiEEPJp (ORCPT ); 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05 May 2022 08:05:11 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:05:11 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 5 May 2022 08:05:07 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v14 4/4] arm64: dts: qcom: sc7280-herobrine: Add lpi pinmux properties for CRD 3.0/3.1 Date: Thu, 5 May 2022 20:33:24 +0530 Message-ID: <1651763004-32533-5-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> References: <1651763004-32533-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LPASS LPI pinctrl properties, which are required for Audio functionality on herobrine based platforms of rev5+ (aka CRD 3.0/3.1) boards. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 61 +++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64= /boot/dts/qcom/sc7280-herobrine-crd.dts index deaea3a..3cce107 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -110,6 +110,67 @@ ap_ts_pen_1v8: &i2c13 { * - If a pin is totally internal to Qcard then it gets Qcard name. * - If a pin is not hooked up on Qcard, it gets no name. */ +&lpass_dmic01_clk { + drive-strength =3D <8>; + bias-disable; +}; + +&lpass_dmic01_clk_sleep { + drive-strength =3D <2>; +}; + +&lpass_dmic01_data { + bias-pull-down; +}; + +&lpass_dmic23_clk { + drive-strength =3D <8>; + bias-disable; +}; + +&lpass_dmic23_clk_sleep { + drive-strength =3D <2>; +}; + +&lpass_dmic23_data { + bias-pull-down; +}; + +&lpass_rx_swr_clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; +}; + +&lpass_rx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_rx_swr_data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; +}; + +&lpass_rx_swr_data_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; +}; + +&lpass_tx_swr_clk_sleep { + bias-pull-down; +}; + +&lpass_tx_swr_data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; +}; =20 &mi2s1_data0 { drive-strength =3D <6>; --=20 2.7.4