From nobody Fri May 8 11:35:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DA23C433F5 for ; Wed, 4 May 2022 16:15:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353264AbiEDQTc (ORCPT ); Wed, 4 May 2022 12:19:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353239AbiEDQSu (ORCPT ); Wed, 4 May 2022 12:18:50 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51CBF46B2E for ; Wed, 4 May 2022 09:15:12 -0700 (PDT) Date: Wed, 04 May 2022 16:15:09 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1651680911; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YvWUCE05VAUNVaeaG/FzspO0hMzMwVZFzj5zR+dJitE=; b=ro5EkUP3JsJrHWnQX97a7xNzAPmI68rMu1k45m+5H3tW5mA+UzEimaRbZBT9rrvkZGj4kG nSPgBMlux9eGcCZgM+E4DjNXtcgTaFsc/8Cx4W/kw24V/UrM/cCLxxYsklbNVMR1TCsNvR Pr0yij/aEMiQFh+ERl5qUjjEN0ZPCB6k4ZwWyvtoyhqTLqr9NzIsEXSOHpFpjhM3N2yALV qUIJJRvmcxOGEXQRvFdH/7b3K1HK3cqNaHb7qhuKoKllqPNrpdf2h3toJwgNcr9clyP2C6 BQBx6hndkQ+3jSmsJb8s+bQQzPAY+4oi6oZtRBD8H6JL3Acjj8rwPO2M1RVxWQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1651680911; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YvWUCE05VAUNVaeaG/FzspO0hMzMwVZFzj5zR+dJitE=; b=1xLlVyF5yQe+8d9rSzVvavYmxDrtfqVefmqJrGmkSMDDh7uJNU0EvMshOhKwgzmn34N5G8 chB45YcBX6x9rHDg== From: "irqchip-bot for Nathan Rossi" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/armada-370-xp: Enable MSI affinity configuration Cc: Nathan Rossi , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220422043532.146946-1-nathan@nathanrossi.com> References: <20220422043532.146946-1-nathan@nathanrossi.com> MIME-Version: 1.0 Message-ID: <165168090984.4207.14744416156306479417.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 8ca61cde32c1db778aa52631184484e051cbdf27 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/8ca61cde32c1db778aa52631184484e051cbdf27 Author: Nathan Rossi AuthorDate: Fri, 22 Apr 2022 04:35:32=20 Committer: Marc Zyngier CommitterDate: Wed, 04 May 2022 16:40:06 +01:00 irqchip/armada-370-xp: Enable MSI affinity configuration With multiple devices attached via PCIe to an Armada 385 it is possible to overwhelm a single CPU with MSI interrupts. Under certain scenarios configuring the interrupts to be handled by more than one CPU would prevent the system from being overwhelmed. However the irqchip-aramada-370-xp driver is configured to only handle MSIs on the boot CPU, and provides no affinity configuration. This change adds support to the armada-370-xp driver to allow for configuring the affinity of specific MSI irqs and to generate the interrupts on secondary CPUs. This is done by enabling the private doorbell for all online CPUs and configures all CPUs to unmask MSI specific private doorbell bits. The CPU affinity selection of the interrupt is handled by the target list of the software triggered interrupt value, which is provided as the MSI message. The message has the associated CPU bit set for the target CPU. For private doorbell interrupts only one bit can be set otherwise all CPUs will receive the interrupt, so the lowest CPU in the affinity mask is used. This means that by default the first CPU will handle all the interrupts as was the case before. Signed-off-by: Nathan Rossi Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220422043532.146946-1-nathan@nathanrossi.= com --- drivers/irqchip/irq-armada-370-xp.c | 45 ++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-arma= da-370-xp.c index 5b8d571..c877285 100644 --- a/drivers/irqchip/irq-armada-370-xp.c +++ b/drivers/irqchip/irq-armada-370-xp.c @@ -209,15 +209,29 @@ static struct msi_domain_info armada_370_xp_msi_domai= n_info =3D { =20 static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct ms= i_msg *msg) { + unsigned int cpu =3D cpumask_first(irq_data_get_effective_affinity_mask(d= ata)); + msg->address_lo =3D lower_32_bits(msi_doorbell_addr); msg->address_hi =3D upper_32_bits(msi_doorbell_addr); - msg->data =3D 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START); + msg->data =3D BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START); } =20 static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force) { - return -EINVAL; + unsigned int cpu; + + if (!force) + cpu =3D cpumask_any_and(mask, cpu_online_mask); + else + cpu =3D cpumask_first(mask); + + if (cpu >=3D nr_cpu_ids) + return -EINVAL; + + irq_data_update_effective_affinity(irq_data, cpumask_of(cpu)); + + return IRQ_SET_MASK_OK; } =20 static struct irq_chip armada_370_xp_msi_bottom_irq_chip =3D { @@ -264,11 +278,21 @@ static const struct irq_domain_ops armada_370_xp_msi_= domain_ops =3D { .free =3D armada_370_xp_msi_free, }; =20 -static int armada_370_xp_msi_init(struct device_node *node, - phys_addr_t main_int_phys_base) +static void armada_370_xp_msi_reenable_percpu(void) { u32 reg; =20 + /* Enable MSI doorbell mask and combined cpu local interrupt */ + reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) + | PCI_MSI_DOORBELL_MASK; + writel(reg, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS); + /* Unmask local doorbell interrupt */ + writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); +} + +static int armada_370_xp_msi_init(struct device_node *node, + phys_addr_t main_int_phys_base) +{ msi_doorbell_addr =3D main_int_phys_base + ARMADA_370_XP_SW_TRIG_INT_OFFS; =20 @@ -287,18 +311,13 @@ static int armada_370_xp_msi_init(struct device_node = *node, return -ENOMEM; } =20 - reg =3D readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS) - | PCI_MSI_DOORBELL_MASK; - - writel(reg, per_cpu_int_base + - ARMADA_370_XP_IN_DRBEL_MSK_OFFS); - - /* Unmask IPI interrupt */ - writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); + armada_370_xp_msi_reenable_percpu(); =20 return 0; } #else +static void armada_370_xp_msi_reenable_percpu(void) {} + static inline int armada_370_xp_msi_init(struct device_node *node, phys_addr_t main_int_phys_base) { @@ -501,6 +520,8 @@ static void armada_xp_mpic_reenable_percpu(void) } =20 ipi_resume(); + + armada_370_xp_msi_reenable_percpu(); } =20 static int armada_xp_mpic_starting_cpu(unsigned int cpu)