From nobody Sun May 10 14:20:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CAD2C433EF for ; Mon, 2 May 2022 17:08:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386462AbiEBRL5 (ORCPT ); Mon, 2 May 2022 13:11:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382436AbiEBRLy (ORCPT ); Mon, 2 May 2022 13:11:54 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D56C2BD7; Mon, 2 May 2022 10:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651511305; x=1683047305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=AR3nROx9kSazZj+h7yJIP1c+hNRzoH3odyY+rnljXck=; b=XuVYe/40Gs8oIqhQP7N11o3QMEAu9kMBr5eKJUFbVH1oXGbCAScnerfm rjJhS3mZuomrtVeCBbI4CcLmyeYsxcH3vf8Wxqyu/VdUebpcD+kfpc8sN EKx2E/5enxVirwSYCgCXXPjTGxE/sjOZiCS8LTacsiR3GAq3tewpmyJou c=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 02 May 2022 10:08:25 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 10:08:25 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:24 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:21 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v3 1/4] ARM: dts: qcom: sdx65: Add QPIC BAM support Date: Mon, 2 May 2022 10:08:03 -0700 Message-ID: <1651511286-18690-2-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index a64be20..d6a6087 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -199,6 +199,18 @@ qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + qpic_bam: dma-controller@1b04000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x01b04000 0x1c000>; + interrupts =3D ; + clocks =3D <&rpmhcc RPMH_QPIC_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + qcom,controlled-remotely; + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x01f40000 0x40000>; --=20 2.7.4 From nobody Sun May 10 14:20:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 051D9C433EF for ; Mon, 2 May 2022 17:08:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386510AbiEBRMD (ORCPT ); Mon, 2 May 2022 13:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349891AbiEBRL6 (ORCPT ); Mon, 2 May 2022 13:11:58 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F18682DC6; Mon, 2 May 2022 10:08:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651511309; x=1683047309; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=48+rVERvNTQxNqzw5fqv4Nm35unnocBFemLJibc0Q54=; b=eaDLduCHjl8YK3YdXBwwU/FX9Ma6+CUlAig76XPJJbezjjwNx6UzoKHV Dc+LpP268WdoK2aIv3lB5nEWmmj+7ZThA7q/lKl0XQLEtJIXpeVqFXyIm 2MrMcjfNtfMCR9f5MMpk24SLL6GLhwZ+FecsX9f/4S8iZdVZNRNEajd2O A=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 02 May 2022 10:08:29 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 10:08:28 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:28 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:24 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v3 2/4] ARM: dts: qcom: sdx65: Add QPIC NAND support Date: Mon, 2 May 2022 10:08:04 -0700 Message-ID: <1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index d6a6087..a75e9f1 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ clock-output-names =3D "sleep_clk"; #clock-cells =3D <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; }; =20 cpus { @@ -211,6 +217,22 @@ status =3D "disabled"; }; =20 + qpic_nand: nand-controller@1b30000 { + compatible =3D "qcom,sdx55-nand"; + reg =3D <0x01b30000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names =3D "core", "aon"; + + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", "rx", "cmd"; + status =3D "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x01f40000 0x40000>; --=20 2.7.4 From nobody Sun May 10 14:20:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9668C433FE for ; Mon, 2 May 2022 17:08:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386531AbiEBRMH (ORCPT ); Mon, 2 May 2022 13:12:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1386481AbiEBRMC (ORCPT ); Mon, 2 May 2022 13:12:02 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A0315F69; Mon, 2 May 2022 10:08:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651511312; x=1683047312; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PbE3GPQshf1vk3gSrYBDP/zHB5ltThgg9HvxWrWwRWI=; b=A4PbLXod+wN/cP/Mu5fJCBS9sjz89lgdcr0I6RCvHVsfn6cdR29NMa+l bpJwtnvQm045Vv5VboXUD4/CCGhAGEAaMBHqJmqu6uq87NXQrnrj9oDhR RsdAcZDETbig6+tyeKCRgtcz2KPCe/4uOvpsyi2zkSN/aB1G9oHcLJycq U=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-01.qualcomm.com with ESMTP; 02 May 2022 10:08:31 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 10:08:31 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:31 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:28 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v3 3/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support Date: Mon, 2 May 2022 10:08:05 -0700 Message-ID: <1651511286-18690-4-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable QPIC BAM devicetree node for Qualcomm SDX65-MTP board. While at it, sort the blsp1_uart3 node in alphabetical order and set it's status as "okay". Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-= sdx65-mtp.dts index 6920524..e9c8df9 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -64,10 +64,6 @@ }; }; =20 -&blsp1_uart3 { - status =3D "ok"; -}; - &apps_rsc { pmx65-rpmh-regulators { compatible =3D "qcom,pmx65-rpmh-regulators"; @@ -245,6 +241,14 @@ }; }; =20 +&blsp1_uart3 { + status =3D "okay"; +}; + +&qpic_bam { + status =3D "okay"; +}; + &usb { status =3D "okay"; }; --=20 2.7.4 From nobody Sun May 10 14:20:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C60CC433F5 for ; Mon, 2 May 2022 17:08:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1386534AbiEBRML (ORCPT ); Mon, 2 May 2022 13:12:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1386499AbiEBRME (ORCPT ); Mon, 2 May 2022 13:12:04 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82D285F55; Mon, 2 May 2022 10:08:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1651511315; x=1683047315; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=pSD3GbcUt2xtT95+6XWgExlKRKxHZVzndq557b9Kp+8=; b=Dgbsluk5UdZsls5BZCvtc7jJceFJIonjcy+jl6UFGb3FFB/b9pLXf7Oo H6X1jNmKWAu2y1mmzre7SQ9XxYZn+ZXeVUUSasGSQ7db4Z7fbxIsO7lVy J4uMUJrVj5R6moUWOryKqp4ak2z1d/uUfAioKhXCsn1glw+eV1NCq696g g=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-02.qualcomm.com with ESMTP; 02 May 2022 10:08:35 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 May 2022 10:08:35 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:34 -0700 Received: from kaushalk-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 2 May 2022 10:08:31 -0700 From: Kaushal Kumar To: , , , CC: , , , , "Kaushal Kumar" Subject: [PATCH v3 4/4] ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support Date: Mon, 2 May 2022 10:08:06 -0700 Message-ID: <1651511286-18690-5-git-send-email-quic_kaushalk@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> References: <1651511286-18690-1-git-send-email-quic_kaushalk@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-= sdx65-mtp.dts index e9c8df9..e747ec0 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -249,6 +249,21 @@ status =3D "okay"; }; =20 +&qpic_nand { + status =3D "okay"; + + nand@0 { + reg =3D <0>; + + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + nand-bus-width =3D <8>; + /* ico and efs2 partitions are secured */ + secure-regions =3D /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + &usb { status =3D "okay"; }; --=20 2.7.4