From nobody Thu May 14 08:17:35 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E66BC433EF for ; Tue, 19 Apr 2022 14:29:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353396AbiDSOcA (ORCPT ); Tue, 19 Apr 2022 10:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353325AbiDSObq (ORCPT ); Tue, 19 Apr 2022 10:31:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7630DE0CF for ; Tue, 19 Apr 2022 07:29:03 -0700 (PDT) Date: Tue, 19 Apr 2022 14:29:01 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1650378542; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dwTssSRZcN+l5J78amCyw5v7vRsMj/YExcd2H+0PI1I=; b=OQTBPLdDhgFI/j8jtPz1A6UTaTyFMKo/sULD03fbFEuPkQf1q2393uTcT63UdjOuDkFqYD 51PmjbMPtv8yTaH4qwJB2u/oc5HWLAVESxYNKLbxot/excrvJyee0MlldsOrmjM+W99REg Em9qu3Nrsf/JjViUu0lTQGH5dsYX1bIj/NTZ5+EnRlDcelY/u8Ivuxz6rhcYisEVygRB6I XWF5uCcrwjzbbf6z0KQ/DDfoOJI25jw9JOsm375PN1ROl56zUbDfvYcciVXkZWJ9XPy/Kb lUDduzinNXVby5ITZe/8/Pi0DvyBd9XyBUMDZ737DaxhePM4NVRkhXnfcRgaoA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1650378542; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dwTssSRZcN+l5J78amCyw5v7vRsMj/YExcd2H+0PI1I=; b=qz08UOWTgfBdgtFvpG2n6SsruC67FhqzjfCbcaUSNPIS6KX4IAnB+nZfmcG4je9KHY4QiO LMspPyH8zmfDQ6CA== From: "irqchip-bot for Marc Zyngier" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] pinctrl: msmgpio: Make the irqchip immutable Cc: Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220419141846.598305-8-maz@kernel.org> References: <20220419141846.598305-8-maz@kernel.org> MIME-Version: 1.0 Message-ID: <165037854102.4207.4717736702206993862.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 14dbe186b9d42cbf662eae5a4da14687edbf0edb Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/14dbe186b9d42cbf662eae5a4da14687edbf0edb Author: Marc Zyngier AuthorDate: Tue, 19 Apr 2022 15:18:43 +01:00 Committer: Marc Zyngier CommitterDate: Tue, 19 Apr 2022 15:22:26 +01:00 pinctrl: msmgpio: Make the irqchip immutable Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220419141846.598305-8-maz@kernel.org --- drivers/pinctrl/qcom/pinctrl-msm.c | 53 ++++++++++++++++++----------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index 966ea66..a2abfe9 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -42,7 +42,6 @@ * @chip: gpiochip handle. * @desc: pin controller descriptor * @restart_nb: restart notifier block. - * @irq_chip: irq chip information * @irq: parent irq for the TLMM irq_chip. * @intr_target_use_scm: route irq to application cpu using scm calls * @lock: Spinlock to protect register resources as well @@ -63,7 +62,6 @@ struct msm_pinctrl { struct pinctrl_desc desc; struct notifier_block restart_nb; =20 - struct irq_chip irq_chip; int irq; =20 bool intr_target_use_scm; @@ -868,6 +866,8 @@ static void msm_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); struct msm_pinctrl *pctrl =3D gpiochip_get_data(gc); =20 + gpiochip_enable_irq(gc, d->hwirq); + if (d->parent_data) irq_chip_enable_parent(d); =20 @@ -885,6 +885,8 @@ static void msm_gpio_irq_disable(struct irq_data *d) =20 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) msm_gpio_irq_mask(d); + + gpiochip_disable_irq(gc, d->hwirq); } =20 /** @@ -958,6 +960,14 @@ static void msm_gpio_irq_ack(struct irq_data *d) raw_spin_unlock_irqrestore(&pctrl->lock, flags); } =20 +static void msm_gpio_irq_eoi(struct irq_data *d) +{ + d =3D d->parent_data; + + if (d) + d->chip->irq_eoi(d); +} + static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, unsigned int type) { @@ -1255,6 +1265,26 @@ static bool msm_gpio_needs_valid_mask(struct msm_pin= ctrl *pctrl) return device_property_count_u16(pctrl->dev, "gpios") > 0; } =20 +static const struct irq_chip msm_gpio_irq_chip =3D { + .name =3D "msmgpio", + .irq_enable =3D msm_gpio_irq_enable, + .irq_disable =3D msm_gpio_irq_disable, + .irq_mask =3D msm_gpio_irq_mask, + .irq_unmask =3D msm_gpio_irq_unmask, + .irq_ack =3D msm_gpio_irq_ack, + .irq_eoi =3D msm_gpio_irq_eoi, + .irq_set_type =3D msm_gpio_irq_set_type, + .irq_set_wake =3D msm_gpio_irq_set_wake, + .irq_request_resources =3D msm_gpio_irq_reqres, + .irq_release_resources =3D msm_gpio_irq_relres, + .irq_set_affinity =3D msm_gpio_irq_set_affinity, + .irq_set_vcpu_affinity =3D msm_gpio_irq_set_vcpu_affinity, + .flags =3D (IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | + IRQCHIP_IMMUTABLE), +}; + static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; @@ -1276,22 +1306,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) if (msm_gpio_needs_valid_mask(pctrl)) chip->init_valid_mask =3D msm_gpio_init_valid_mask; =20 - pctrl->irq_chip.name =3D "msmgpio"; - pctrl->irq_chip.irq_enable =3D msm_gpio_irq_enable; - pctrl->irq_chip.irq_disable =3D msm_gpio_irq_disable; - pctrl->irq_chip.irq_mask =3D msm_gpio_irq_mask; - pctrl->irq_chip.irq_unmask =3D msm_gpio_irq_unmask; - pctrl->irq_chip.irq_ack =3D msm_gpio_irq_ack; - pctrl->irq_chip.irq_set_type =3D msm_gpio_irq_set_type; - pctrl->irq_chip.irq_set_wake =3D msm_gpio_irq_set_wake; - pctrl->irq_chip.irq_request_resources =3D msm_gpio_irq_reqres; - pctrl->irq_chip.irq_release_resources =3D msm_gpio_irq_relres; - pctrl->irq_chip.irq_set_affinity =3D msm_gpio_irq_set_affinity; - pctrl->irq_chip.irq_set_vcpu_affinity =3D msm_gpio_irq_set_vcpu_affinity; - pctrl->irq_chip.flags =3D IRQCHIP_MASK_ON_SUSPEND | - IRQCHIP_SET_TYPE_MASKED | - IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; - np =3D of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); if (np) { chip->irq.parent_domain =3D irq_find_matching_host(np, @@ -1300,7 +1314,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) if (!chip->irq.parent_domain) return -EPROBE_DEFER; chip->irq.child_to_parent_hwirq =3D msm_gpio_wakeirq; - pctrl->irq_chip.irq_eoi =3D irq_chip_eoi_parent; /* * Let's skip handling the GPIOs, if the parent irqchip * is handling the direct connect IRQ of the GPIO. @@ -1313,7 +1326,7 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) } =20 girq =3D &chip->irq; - girq->chip =3D &pctrl->irq_chip; + gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip); girq->parent_handler =3D msm_gpio_irq_handler; girq->fwnode =3D pctrl->dev->fwnode; girq->num_parents =3D 1;