From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5084BC433F5 for ; Thu, 14 Apr 2022 12:31:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243352AbiDNMd2 (ORCPT ); Thu, 14 Apr 2022 08:33:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243342AbiDNMdW (ORCPT ); Thu, 14 Apr 2022 08:33:22 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE39D275E3; Thu, 14 Apr 2022 05:30:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939458; x=1681475458; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=Aq8HvzHRB/MIc27qf/VrkpAgx3k8PjsQkDRQBQeNTR4=; b=AIl3Fjl5xSc3jv124aJpQ0kjchL+jn6Hf23jhZ8atckPP/qJT6+00rTa fxAPUCV9iADC5vs8gyCXmX3AeRvNIoTUFv3osk8i5DYgiJyKKt0piT3QR E/u+UCHaJq+YsQFD8S64degaP9TmBXJspkn2f1wtHlrLFR/ITGZ8xAWl0 o=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 14 Apr 2022 05:30:57 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:30:57 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:30:57 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:30:52 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 1/9] dt-bindings: mfd: pm8008: Add reset-gpios Date: Thu, 14 Apr 2022 18:00:10 +0530 Message-ID: <1649939418-19861-2-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add reset-gpios property for pm8008. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Rob Herring --- Changes in V10: - None. Changes in V9: - Undo the changes from V8 and only add reset-gpios. Leave interrupts as required properties and do not change compatible. Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Docum= entation/devicetree/bindings/mfd/qcom,pm8008.yaml index ec3138c..3312784 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -44,6 +44,9 @@ properties: "#size-cells": const: 0 =20 + reset-gpios: + maxItems: 1 + patternProperties: "^gpio@[0-9a-f]+$": type: object @@ -92,6 +95,7 @@ required: - "#address-cells" - "#size-cells" - "#interrupt-cells" + - reset-gpios =20 additionalProperties: false =20 @@ -99,6 +103,7 @@ examples: - | #include #include + #include qupv3_se13_i2c { #address-cells =3D <1>; #size-cells =3D <0>; @@ -113,6 +118,8 @@ examples: interrupt-parent =3D <&tlmm>; interrupts =3D <32 IRQ_TYPE_EDGE_RISING>; =20 + reset-gpios =3D <&pm8350c_gpios 4 GPIO_ACTIVE_HIGH>; + pm8008_gpios: gpio@c000 { compatible =3D "qcom,pm8008-gpio", "qcom,spmi-gpio"; reg =3D <0xc000>; --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FB57C433F5 for ; Thu, 14 Apr 2022 12:31:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243354AbiDNMdf (ORCPT ); Thu, 14 Apr 2022 08:33:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243346AbiDNMd1 (ORCPT ); Thu, 14 Apr 2022 08:33:27 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A68C12FE48; Thu, 14 Apr 2022 05:31:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939462; x=1681475462; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=XJIV+jBdnfLZCgjBHNlwQwCsTaYirvNMpAPl7NJYPY0=; b=Kzx87znmwKOfqew63AWniDk95KHbcRPDSjsLO0NFyvxaRzwfMxGTiNGl oLVyIUd/1GlXDI16SnTjs5RU43nN/cGdREe2qrx6czsybbvECLmmhJMhM 72L7KS2PiG5MFf8cneool9BwSpHbAobhOY3yCew3zUenh0/IvXnMRH/6/ s=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 14 Apr 2022 05:31:02 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:01 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:01 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:30:57 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 2/9] dt-bindings: regulator: pm8008: Add pm8008 regulator bindings Date: Thu, 14 Apr 2022 18:00:11 +0530 Message-ID: <1649939418-19861-3-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for pm8008 regulators. Signed-off-by: Satya Priya Reviewed-by: Rob Herring --- Changes in V8: - This is split from pm8008.yaml binding. Changes in V9: - Remove description for reg and drop unused phandle from example. Changes in V10: - Regulators are added as a part of pm8008@8 device. Change bindings doc accordingly. .../bindings/regulator/qcom,pm8008-regulators.yaml | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/qcom,pm8008= -regulators.yaml diff --git a/Documentation/devicetree/bindings/regulator/qcom,pm8008-regula= tors.yaml b/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulat= ors.yaml new file mode 100644 index 0000000..f56cdcc --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,pm8008-regulators.ya= ml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,pm8008-regulators.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. PM8008 Regulator bindings + +maintainers: + - Satya Priya + +description: | + Qualcomm Technologies, Inc. PM8008 is an I2C controlled PMIC + containing 7 LDO regulators. This binding specifies the PM8008 + regulator peripherals of PM8008 device. + +properties: + vdd_l1_l2-supply: + description: Input supply phandle of ldo1 and ldo2 regulators. + + vdd_l3_l4-supply: + description: Input supply phandle of ldo3 and ldo4 regulators. + + vdd_l5-supply: + description: Input supply phandle of ldo5 regulator. + + vdd_l6-supply: + description: Input supply phandle of ldo6 regulator. + + vdd_l7-supply: + description: Input supply phandle of ldo7 regulator. + +patternProperties: + "^ldo[1-7]$": + type: object + $ref: "/schemas/regulator/regulator.yaml#" + description: PM8008 regulator peripherals of PM8008 regulator device. + +additionalProperties: false +... --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 894AFC433EF for ; Thu, 14 Apr 2022 12:31:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243381AbiDNMdk (ORCPT ); Thu, 14 Apr 2022 08:33:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243371AbiDNMdd (ORCPT ); Thu, 14 Apr 2022 08:33:33 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A7B1340F2; Thu, 14 Apr 2022 05:31:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939466; x=1681475466; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=mol9L4z7TxFFL5K9se+ZnR6/rfEU2d6sk/+M8yAFBRU=; b=C1tVC4QLLQwoA+LL//tkQm7mxAZtAW55m+dr8X0Bkm1RcsuML4lwR/hQ rqWLWsTw6ZwrUC5gwK09UL3teC7UZbGS4dzOQIF5u63y6asZdatJRTyNh CSuozmYCi160Az/OK2l7p+/oytYACX+ehXt4o3w35nmV674/4SJOhFGi7 A=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 14 Apr 2022 05:31:06 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:06 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:05 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:01 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 3/9] dt-bindings: mfd: pm8008: Add regulators Date: Thu, 14 Apr 2022 18:00:12 +0530 Message-ID: <1649939418-19861-4-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add regulators for pm8008 with example. Signed-off-by: Satya Priya Reviewed-by: Rob Herring --- Changes in V10: - Add regulators under main mfd node as in DT. Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml | 17 ++++++++++++++= +++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml b/Docum= entation/devicetree/bindings/mfd/qcom,pm8008.yaml index 3312784..060cc35 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,pm8008.yaml @@ -44,6 +44,9 @@ properties: "#size-cells": const: 0 =20 + regulators: + $ref: "/schemas/regulator/qcom,pm8008-regulators.yaml#" + reset-gpios: maxItems: 1 =20 @@ -129,6 +132,20 @@ examples: interrupt-controller; #interrupt-cells =3D <2>; }; + + regulators { + vdd_l1_l2-supply =3D <&vreg_s8b_1p2>; + vdd_l3_l4-supply =3D <&vreg_s1b_1p8>; + vdd_l5-supply =3D <&vreg_bob>; + vdd_l6-supply =3D <&vreg_bob>; + vdd_l7-supply =3D <&vreg_bob>; + + ldo1 { + regulator-name =3D "pm8008_l1"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1300000>; + }; + }; }; }; =20 --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D46FC433EF for ; Thu, 14 Apr 2022 12:31:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241302AbiDNMdq (ORCPT ); Thu, 14 Apr 2022 08:33:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243388AbiDNMdl (ORCPT ); Thu, 14 Apr 2022 08:33:41 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFCB938195; Thu, 14 Apr 2022 05:31:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939475; x=1681475475; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ittCj7XZJ/CtLmop6fZ5zdHBBalDy7MvV1QbC5uRLII=; b=iVeO9WLFWCdtYUZATJ7dY+kqzu7XAK8qzAcuki/zYrkMZwfU+vJDX4Gw r+sCILAav30E+K1PZfqlCPrnS8FzYmB8RM0G5AG+YdwqigGnhy9qwo0/r OiLdYbMc2jOCvKp0RJZTqDNnaEIFYgu/n2cI8x11ZPs4OHPsIX5UkpCbx s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 14 Apr 2022 05:31:11 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:10 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:10 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:05 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 4/9] mfd: pm8008: Add reset-gpios Date: Thu, 14 Apr 2022 18:00:13 +0530 Message-ID: <1649939418-19861-5-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the reset-gpio toggling in the pm8008_probe() to bring pm8008 chip out of reset instead of doing it in DT node using "output-high" property. Signed-off-by: Satya Priya --- Changes in V10: - This has been split from [V9,3/6] as per comments here [1] [1] https://patchwork.kernel.org/project/linux-arm-msm/patch/1649166633-25= 872-4-git-send-email-quic_c_skakit@quicinc.com/#24803409 drivers/mfd/qcom-pm8008.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index c472d7f..97a72da 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -57,6 +58,7 @@ enum { struct pm8008_data { struct device *dev; struct regmap *regmap; + struct gpio_desc *reset_gpio; int irq; struct regmap_irq_chip_data *irq_data; }; @@ -239,6 +241,13 @@ static int pm8008_probe(struct i2c_client *client) dev_err(chip->dev, "Failed to probe irq periphs: %d\n", rc); } =20 + chip->reset_gpio =3D devm_gpiod_get(chip->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(chip->reset_gpio)) { + dev_err(chip->dev, "failed to acquire reset gpio\n"); + return PTR_ERR(chip->reset_gpio); + } + gpiod_set_value(chip->reset_gpio, 1); + return devm_of_platform_populate(chip->dev); } =20 --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60150C433F5 for ; Thu, 14 Apr 2022 12:31:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243382AbiDNMdx (ORCPT ); Thu, 14 Apr 2022 08:33:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243366AbiDNMdm (ORCPT ); Thu, 14 Apr 2022 08:33:42 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B2A738DBA; Thu, 14 Apr 2022 05:31:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939476; x=1681475476; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=9DQByKwtwdgnOvqCSn20bztLHUzukxppsLyV8wP5/a4=; b=TsT/C6dmj52D5AUCuVcibW7jqZCqw47o5iV2+bAkeFLOM645RWjIhNJ5 XG6RNOc9NEyz0N3zH0xboxfEEHPcjvtlkJBkLyrpfeOuVbMtQ/sgwhD+d gngfSZjndFEMg6VcIT8a2BSWeTZZnDJL4cK4ekqRA90gUrbTclHgeYJWL I=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 14 Apr 2022 05:31:15 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:15 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:14 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:10 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 5/9] mfd: pm8008: Use i2c_new_dummy_device() API Date: Thu, 14 Apr 2022 18:00:14 +0530 Message-ID: <1649939418-19861-6-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use i2c_new_dummy_device() to register clients along with the main mfd device. Signed-off-by: Satya Priya --- Changes in V10: - Implement i2c_new_dummy_device to register extra clients. drivers/mfd/qcom-pm8008.c | 54 +++++++++++++++++++++++++++++++++----= ---- include/linux/mfd/qcom_pm8008.h | 13 ++++++++++ 2 files changed, 57 insertions(+), 10 deletions(-) create mode 100644 include/linux/mfd/qcom_pm8008.h diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index 97a72da..ca5240d 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -56,8 +57,10 @@ enum { #define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) =20 struct pm8008_data { + bool ready; struct device *dev; - struct regmap *regmap; + struct i2c_client *clients[PM8008_NUM_CLIENTS]; + struct regmap *regmap[PM8008_NUM_CLIENTS]; struct gpio_desc *reset_gpio; int irq; struct regmap_irq_chip_data *irq_data; @@ -152,9 +155,20 @@ static struct regmap_config qcom_mfd_regmap_cfg =3D { .max_register =3D 0xFFFF, }; =20 +struct regmap *pm8008_get_regmap(struct pm8008_data *chip, u8 sid) +{ + if (!chip || !chip->ready) { + pr_err("pm8008 chip not initialized\n"); + return NULL; + } + + return chip->regmap[sid]; +} + static int pm8008_init(struct pm8008_data *chip) { int rc; + struct regmap *regmap =3D pm8008_get_regmap(chip, PM8008_INFRA_SID); =20 /* * Set TEMP_ALARM peripheral's TYPE so that the regmap-irq framework @@ -162,19 +176,19 @@ static int pm8008_init(struct pm8008_data *chip) * This is required to enable the writing of TYPE registers in * regmap_irq_sync_unlock(). */ - rc =3D regmap_write(chip->regmap, + rc =3D regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); if (rc) return rc; =20 /* Do the same for GPIO1 and GPIO2 peripherals */ - rc =3D regmap_write(chip->regmap, + rc =3D regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); if (rc) return rc; =20 - rc =3D regmap_write(chip->regmap, + rc =3D regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0)); =20 return rc; @@ -186,6 +200,7 @@ static int pm8008_probe_irq_peripherals(struct pm8008_d= ata *chip, int rc, i; struct regmap_irq_type *type; struct regmap_irq_chip_data *irq_data; + struct regmap *regmap =3D pm8008_get_regmap(chip, PM8008_INFRA_SID); =20 rc =3D pm8008_init(chip); if (rc) { @@ -209,7 +224,7 @@ static int pm8008_probe_irq_peripherals(struct pm8008_d= ata *chip, IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); } =20 - rc =3D devm_regmap_add_irq_chip(chip->dev, chip->regmap, client_irq, + rc =3D devm_regmap_add_irq_chip(chip->dev, regmap, client_irq, IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data); if (rc) { dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc); @@ -221,19 +236,38 @@ static int pm8008_probe_irq_peripherals(struct pm8008= _data *chip, =20 static int pm8008_probe(struct i2c_client *client) { - int rc; + int rc, i; struct pm8008_data *chip; + struct device_node *node =3D client->dev.of_node; =20 chip =3D devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); if (!chip) return -ENOMEM; =20 chip->dev =3D &client->dev; - chip->regmap =3D devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg); - if (!chip->regmap) - return -ENODEV; =20 - i2c_set_clientdata(client, chip); + for (i =3D 0; i < PM8008_NUM_CLIENTS; i++) { + if (i =3D=3D 0) { + chip->clients[i] =3D client; + } else { + chip->clients[i] =3D i2c_new_dummy_device(client->adapter, + client->addr + i); + if (IS_ERR(chip->clients[i])) { + dev_err(&client->dev, "can't attach client %d\n", i); + return PTR_ERR(chip->clients[i]); + } + chip->clients[i]->dev.of_node =3D of_node_get(node); + } + + chip->regmap[i] =3D devm_regmap_init_i2c(chip->clients[i], + &qcom_mfd_regmap_cfg); + if (!chip->regmap[i]) + return -ENODEV; + + i2c_set_clientdata(chip->clients[i], chip); + } + + chip->ready =3D true; =20 if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) { rc =3D pm8008_probe_irq_peripherals(chip, client->irq); diff --git a/include/linux/mfd/qcom_pm8008.h b/include/linux/mfd/qcom_pm800= 8.h new file mode 100644 index 0000000..bc64f01 --- /dev/null +++ b/include/linux/mfd/qcom_pm8008.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __QCOM_PM8008_H__ +#define __QCOM_PM8008_H__ + +#define PM8008_INFRA_SID 0 +#define PM8008_REGULATORS_SID 1 + +#define PM8008_NUM_CLIENTS 2 + +struct pm8008_data; +struct regmap *pm8008_get_regmap(struct pm8008_data *chip, u8 sid); + +#endif --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0093BC433EF for ; Thu, 14 Apr 2022 12:31:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243429AbiDNMeO (ORCPT ); Thu, 14 Apr 2022 08:34:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243391AbiDNMdp (ORCPT ); Thu, 14 Apr 2022 08:33:45 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D55953A5F5; Thu, 14 Apr 2022 05:31:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; 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Thu, 14 Apr 2022 05:31:14 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 6/9] mfd: pm8008: Add mfd_cell struct to register LDOs Date: Thu, 14 Apr 2022 18:00:15 +0530 Message-ID: <1649939418-19861-7-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add mfd_cell struct to probe LDO regulators using devm_mfd_add_devices() API. Signed-off-by: Satya Priya --- Changes in V8: - Split the probe for infra and regulator devices - Add the reset-gpio toggling in the infra driver probe Changes in V9: - Fixed nits. Changes in V10: - Removed the extra probe added for regulators as is is not needed now. drivers/mfd/qcom-pm8008.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mfd/qcom-pm8008.c b/drivers/mfd/qcom-pm8008.c index ca5240d..ab4ba55 100644 --- a/drivers/mfd/qcom-pm8008.c +++ b/drivers/mfd/qcom-pm8008.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -29,6 +30,10 @@ #define INT_EN_CLR_OFFSET 0x16 #define INT_LATCHED_STS_OFFSET 0x18 =20 +static const struct mfd_cell pm8008_regulator_devs[] =3D { + MFD_CELL_NAME("qcom-pm8008-regulator"), +}; + enum { PM8008_MISC, PM8008_TEMP_ALARM, @@ -282,6 +287,14 @@ static int pm8008_probe(struct i2c_client *client) } gpiod_set_value(chip->reset_gpio, 1); =20 + rc =3D devm_mfd_add_devices(&chip->clients[PM8008_REGULATORS_SID]->dev, + 0, pm8008_regulator_devs, ARRAY_SIZE(pm8008_regulator_devs), + NULL, 0, NULL); + if (rc) { + dev_err(chip->dev, "Failed to add regulators: %d\n", rc); + return rc; + } + return devm_of_platform_populate(chip->dev); } =20 --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24942C433FE for ; Thu, 14 Apr 2022 12:31:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232000AbiDNMeJ (ORCPT ); Thu, 14 Apr 2022 08:34:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243359AbiDNMdu (ORCPT ); Thu, 14 Apr 2022 08:33:50 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37A936A406; Thu, 14 Apr 2022 05:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939484; x=1681475484; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=FA08h66lN49U/fbSLY5Q9IrW4iiDmrwj4AhevBP6sY4=; b=Twd91EwRjOWLyqoThXhZyrQkcMxIgefN1Q8R2OX3bMJPgbqRQ2/JjwTa SSxD6ylzNCIv8TRpHIQPxKkSrdUhoXz+kd6wlPprx7OonPIPxr0JZ8Rca yy/bnYnsrtJJGxU4LsSbs5HfRl4F36L/k7ozBVyXpqjMslEBViufOVGyp c=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 14 Apr 2022 05:31:24 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:23 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:23 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:19 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 7/9] regulator: Add a regulator driver for the PM8008 PMIC Date: Thu, 14 Apr 2022 18:00:16 +0530 Message-ID: <1649939418-19861-8-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Qualcomm Technologies, Inc. PM8008 is an I2C controlled PMIC containing 7 LDO regulators. Add a PM8008 regulator driver to support PMIC regulator management via the regulator framework. Signed-off-by: Satya Priya --- Changes in V8: - Changed the regulators_data struct name to pm8008_regulator_data Changes in V9: - Nothing has changed. Changes in V10: - Changed the driver name. - Removed unused header. - Use get_voltage_sel. drivers/regulator/Kconfig | 9 ++ drivers/regulator/Makefile | 1 + drivers/regulator/qcom-pm8008-regulator.c | 201 ++++++++++++++++++++++++++= ++++ 3 files changed, 211 insertions(+) create mode 100644 drivers/regulator/qcom-pm8008-regulator.c diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index a7effc5..ce8522d 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -925,6 +925,15 @@ config REGULATOR_PWM This driver supports PWM controlled voltage regulators. PWM duty cycle can increase or decrease the voltage. =20 +config REGULATOR_QCOM_PM8008 + tristate "Qualcomm Technologies, Inc. PM8008 PMIC regulators" + depends on MFD_QCOM_PM8008 + help + Select this option to get support for the voltage regulators + of Qualcomm Technologies, Inc. PM8008 PMIC chip. PM8008 has 7 LDO + regulators. This driver provides support for basic operations like + set/get voltage and enable/disable. + config REGULATOR_QCOM_RPM tristate "Qualcomm RPM regulator driver" depends on MFD_QCOM_RPM diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 69b5a19..fc045d9 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -101,6 +101,7 @@ obj-$(CONFIG_REGULATOR_MT6380) +=3D mt6380-regulator.o obj-$(CONFIG_REGULATOR_MT6397) +=3D mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) +=3D mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) +=3D qcom-labibb-regulator.o +obj-$(CONFIG_REGULATOR_QCOM_PM8008) +=3D qcom-pm8008-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPM) +=3D qcom_rpm-regulator.o obj-$(CONFIG_REGULATOR_QCOM_RPMH) +=3D qcom-rpmh-regulator.o obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) +=3D qcom_smd-regulator.o diff --git a/drivers/regulator/qcom-pm8008-regulator.c b/drivers/regulator/= qcom-pm8008-regulator.c new file mode 100644 index 0000000..4375ac5 --- /dev/null +++ b/drivers/regulator/qcom-pm8008-regulator.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VSET_STEP_MV 8 +#define VSET_STEP_UV (VSET_STEP_MV * 1000) + +#define LDO_ENABLE_REG(base) ((base) + 0x46) +#define ENABLE_BIT BIT(7) + +#define LDO_VSET_LB_REG(base) ((base) + 0x40) + +#define LDO_STEPPER_CTL_REG(base) ((base) + 0x3b) +#define DEFAULT_VOLTAGE_STEPPER_RATE 38400 +#define STEP_RATE_MASK GENMASK(1, 0) + +struct pm8008_regulator_data { + const char *name; + const char *supply_name; + u16 base; + int min_uv; + int max_uv; + int min_dropout_uv; + const struct linear_range *voltage_range; +}; + +struct pm8008_regulator { + struct device *dev; + struct regmap *regmap; + struct regulator_desc rdesc; + u16 base; + int step_rate; + int voltage_selector; +}; + +static const struct linear_range nldo_ranges[] =3D { + REGULATOR_LINEAR_RANGE(528000, 0, 122, 8000), +}; + +static const struct linear_range pldo_ranges[] =3D { + REGULATOR_LINEAR_RANGE(1504000, 0, 237, 8000), +}; + +static const struct pm8008_regulator_data reg_data[] =3D { + /* name parent base min_uv max_uv headroom_uv voltage_range */ + { "ldo1", "vdd_l1_l2", 0x4000, 528000, 1504000, 225000, nldo_ranges, }, + { "ldo2", "vdd_l1_l2", 0x4100, 528000, 1504000, 225000, nldo_ranges, }, + { "ldo3", "vdd_l3_l4", 0x4200, 1504000, 3400000, 300000, pldo_ranges, }, + { "ldo4", "vdd_l3_l4", 0x4300, 1504000, 3400000, 300000, pldo_ranges, }, + { "ldo5", "vdd_l5", 0x4400, 1504000, 3400000, 200000, pldo_ranges, }, + { "ldo6", "vdd_l6", 0x4500, 1504000, 3400000, 200000, pldo_ranges, }, + { "ldo7", "vdd_l7", 0x4600, 1504000, 3400000, 200000, pldo_ranges, }, +}; + +static int pm8008_regulator_get_voltage(struct regulator_dev *rdev) +{ + struct pm8008_regulator *pm8008_reg =3D rdev_get_drvdata(rdev); + + return pm8008_reg->voltage_selector; +} + +static inline int pm8008_write_voltage(struct pm8008_regulator *pm8008_reg, + int mV) +{ + __le16 vset_raw; + + vset_raw =3D cpu_to_le16(mV); + + return regmap_bulk_write(pm8008_reg->regmap, + LDO_VSET_LB_REG(pm8008_reg->base), + (const void *)&vset_raw, sizeof(vset_raw)); +} + +static int pm8008_regulator_set_voltage_time(struct regulator_dev *rdev, + int old_uV, int new_uv) +{ + struct pm8008_regulator *pm8008_reg =3D rdev_get_drvdata(rdev); + + return DIV_ROUND_UP(abs(new_uv - old_uV), pm8008_reg->step_rate); +} + +static int pm8008_regulator_set_voltage(struct regulator_dev *rdev, + unsigned int selector) +{ + struct pm8008_regulator *pm8008_reg =3D rdev_get_drvdata(rdev); + int rc, mV; + + /* voltage control register is set with voltage in millivolts */ + mV =3D DIV_ROUND_UP(regulator_list_voltage_linear_range(rdev, selector), + 1000); + if (mV < 0) + return mV; + + rc =3D pm8008_write_voltage(pm8008_reg, mV); + if (rc < 0) + return rc; + + pm8008_reg->voltage_selector =3D selector; + dev_dbg(&rdev->dev, "voltage set to %d\n", mV * 1000); + return 0; +} + +static const struct regulator_ops pm8008_regulator_ops =3D { + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_voltage_sel =3D pm8008_regulator_set_voltage, + .get_voltage_sel =3D pm8008_regulator_get_voltage, + .list_voltage =3D regulator_list_voltage_linear, + .set_voltage_time =3D pm8008_regulator_set_voltage_time, +}; + +static int pm8008_regulator_probe(struct platform_device *pdev) +{ + struct pm8008_data *chip =3D dev_get_drvdata(pdev->dev.parent); + struct device *dev =3D &pdev->dev; + struct regulator_dev *rdev; + struct pm8008_regulator *pm8008_reg; + struct regmap *regmap; + struct regulator_config reg_config =3D {}; + int rc, i; + unsigned int reg; + + regmap =3D pm8008_get_regmap(chip, PM8008_REGULATORS_SID); + if (!regmap) { + dev_err(dev, "parent regmap is missing\n"); + return -EINVAL; + } + + for (i =3D 0; i < ARRAY_SIZE(reg_data); i++) { + pm8008_reg =3D devm_kzalloc(dev, sizeof(*pm8008_reg), GFP_KERNEL); + if (!pm8008_reg) + return -ENOMEM; + + pm8008_reg->regmap =3D regmap; + pm8008_reg->dev =3D dev; + pm8008_reg->base =3D reg_data[i].base; + + /* get slew rate */ + rc =3D regmap_bulk_read(pm8008_reg->regmap, + LDO_STEPPER_CTL_REG(pm8008_reg->base), ®, 1); + if (rc < 0) { + dev_err(dev, "failed to read step rate configuration rc=3D%d\n", rc); + return rc; + } + reg &=3D STEP_RATE_MASK; + pm8008_reg->step_rate =3D DEFAULT_VOLTAGE_STEPPER_RATE >> reg; + + pm8008_reg->rdesc.type =3D REGULATOR_VOLTAGE; + pm8008_reg->rdesc.ops =3D &pm8008_regulator_ops; + pm8008_reg->rdesc.name =3D reg_data[i].name; + pm8008_reg->rdesc.supply_name =3D reg_data[i].supply_name; + pm8008_reg->rdesc.of_match =3D reg_data[i].name; + pm8008_reg->rdesc.uV_step =3D VSET_STEP_UV; + pm8008_reg->rdesc.min_uV =3D reg_data[i].min_uv; + pm8008_reg->rdesc.n_voltages + =3D ((reg_data[i].max_uv - reg_data[i].min_uv) + / pm8008_reg->rdesc.uV_step) + 1; + pm8008_reg->rdesc.linear_ranges =3D reg_data[i].voltage_range; + pm8008_reg->rdesc.n_linear_ranges =3D 1; + pm8008_reg->rdesc.enable_reg =3D LDO_ENABLE_REG(pm8008_reg->base); + pm8008_reg->rdesc.enable_mask =3D ENABLE_BIT; + pm8008_reg->rdesc.min_dropout_uV =3D reg_data[i].min_dropout_uv; + pm8008_reg->voltage_selector =3D -ENOTRECOVERABLE; + pm8008_reg->rdesc.regulators_node =3D of_match_ptr("regulators"); + + reg_config.dev =3D dev->parent; + reg_config.driver_data =3D pm8008_reg; + + rdev =3D devm_regulator_register(dev, &pm8008_reg->rdesc, ®_config); + if (IS_ERR(rdev)) { + rc =3D PTR_ERR(rdev); + dev_err(dev, "%s: failed to register regulator rc=3D%d\n", + reg_data[i].name, rc); + return rc; + } + } + + return 0; +} + +static struct platform_driver pm8008_regulator_driver =3D { + .driver =3D { + .name =3D "qcom-pm8008-regulator", + }, + .probe =3D pm8008_regulator_probe, +}; + +module_platform_driver(pm8008_regulator_driver); + +MODULE_DESCRIPTION("Qualcomm PM8008 PMIC Regulator Driver"); +MODULE_LICENSE("GPL"); --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 289E1C433F5 for ; Thu, 14 Apr 2022 12:31:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243383AbiDNMeE (ORCPT ); Thu, 14 Apr 2022 08:34:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52984 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232000AbiDNMdx (ORCPT ); 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Thu, 14 Apr 2022 05:31:27 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:23 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 8/9] arm64: dts: qcom: pm8008: Add base dts file Date: Thu, 14 Apr 2022 18:00:17 +0530 Message-ID: <1649939418-19861-9-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add base DTS file for pm8008. Signed-off-by: Satya Priya --- Changes in V9: - Add single dt file for pm8008 instead of adding files like in V8. Changes in V10: - Add regulators under pm8008@8 i.e main mfd node. arch/arm64/boot/dts/qcom/pm8008.dtsi | 42 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8008.dtsi diff --git a/arch/arm64/boot/dts/qcom/pm8008.dtsi b/arch/arm64/boot/dts/qco= m/pm8008.dtsi new file mode 100644 index 0000000..7b4fe68 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8008.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: BSD-3-Clause +// Copyright (c) 2022, The Linux Foundation. All rights reserved. + +&pm8008_bus { + pm8008: pmic@8 { + compatible =3D "qcom,pm8008"; + reg =3D <0x8>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #interrupt-cells =3D <2>; + + pm8008_regulators: regulators { + pm8008_l1: ldo1 { + regulator-name =3D "pm8008_l1"; + }; + + pm8008_l2: ldo2 { + regulator-name =3D "pm8008_l2"; + }; + + pm8008_l3: ldo3 { + regulator-name =3D "pm8008_l3"; + }; + + pm8008_l4: ldo4 { + regulator-name =3D "pm8008_l4"; + }; + + pm8008_l5: ldo5 { + regulator-name =3D "pm8008_l5"; + }; + + pm8008_l6: ldo6 { + regulator-name =3D "pm8008_l6"; + }; + + pm8008_l7: ldo7 { + regulator-name =3D "pm8008_l7"; + }; + }; + }; +}; --=20 2.7.4 From nobody Thu Jun 18 20:12:46 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29C59C433EF for ; Thu, 14 Apr 2022 12:31:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243465AbiDNMeT (ORCPT ); Thu, 14 Apr 2022 08:34:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243403AbiDNMd7 (ORCPT ); Thu, 14 Apr 2022 08:33:59 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0AD38F992; Thu, 14 Apr 2022 05:31:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649939492; x=1681475492; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=E4AvG908UPC+5J4XlCcovfwdNYIlEJIS8e+cJaSBz/g=; b=d5Pi3+uknJVp7lvJk24mN2VUVFB1zWpSl5j3P9LonM0pyc8TtafwVOeF p9Uq/A6aNNUHjjcIh8WE/aBz21nPyJIYGYSBz2I1rcbfj0ZHUOCKZD9sG BUsCA/ub3Ud26jB9o/MH1H6bBGs/i4FGr0W76w1gjSskovXxOrzga1gcr s=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 14 Apr 2022 05:31:32 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2022 05:31:32 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:32 -0700 Received: from c-skakit-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 05:31:27 -0700 From: Satya Priya To: Bjorn Andersson , Rob Herring CC: Lee Jones , Liam Girdwood , Mark Brown , , , , , , , , Satya Priya Subject: [PATCH V10 9/9] arm64: dts: qcom: sc7280: Add pm8008 support for sc7280-idp Date: Thu, 14 Apr 2022 18:00:18 +0530 Message-ID: <1649939418-19861-10-git-send-email-quic_c_skakit@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> References: <1649939418-19861-1-git-send-email-quic_c_skakit@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pm8008 infra and regulators support for sc7280 idp. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd --- Changes in V8: - Add an extra phandle "pm8008_bus" and then include pm8008 dtsi files ins= ide it. - Remove output-high from pm8008_active node. Changes in V9: - Added interrupts properties. Changes in V10: - None. arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 68 ++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 015a347..a834476 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -263,6 +263,65 @@ }; }; =20 +pm8008_bus: &i2c1 { + status =3D "okay"; +}; + +#include "pm8008.dtsi" + +&pm8008 { + interrupt-parent =3D <&tlmm>; + interrupts =3D <24 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pm8008_active>; + + reset-gpios =3D <&pm8350c_gpios 4 GPIO_ACTIVE_HIGH>; +}; + +&pm8008_regulators { + vdd_l1_l2-supply =3D <&vreg_s8b_1p2>; + vdd_l3_l4-supply =3D <&vreg_s1b_1p8>; + vdd_l5-supply =3D <&vreg_bob>; + vdd_l6-supply =3D <&vreg_bob>; + vdd_l7-supply =3D <&vreg_bob>; +}; + +&pm8008_l1 { + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1300000>; +}; + +&pm8008_l2 { + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1250000>; +}; + +&pm8008_l3 { + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3000000>; +}; + +&pm8008_l4 { + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <1600000>; +}; + +&pm8008_l5 { + regulator-min-microvolt =3D <2600000>; + regulator-max-microvolt =3D <3000000>; +}; + +&pm8008_l6 { + regulator-min-microvolt =3D <2600000>; + regulator-max-microvolt =3D <3000000>; +}; + +&pm8008_l7 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; +}; + &qfprom { vcc-supply =3D <&vreg_l1c_1p8>; }; @@ -375,6 +434,15 @@ drive-strength =3D <2>; }; =20 +&pm8350c_gpios { + pm8008_active: pm8008-active { + pins =3D "gpio4"; + function =3D "normal"; + bias-disable; + power-source =3D <0>; + }; +}; + &qspi_cs0 { bias-disable; }; --=20 2.7.4