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Thu, 14 Apr 2022 01:25:44 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 1/6] dt-bindings: timer: Add Tegra186 & Tegra234 Timer Date: Thu, 14 Apr 2022 13:55:33 +0530 Message-ID: <1649924738-17990-2-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9a5da73c-aa77-4628-2116-08da1df0627a X-MS-TrafficTypeDiagnostic: BYAPR12MB2647:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hyPvy4B4Qvo9ruAhjFiMqCXW+YrWXk+0ikgZbHU4w7/Cao+R0JbiBzywNoshAEFXXD4R8NZ8jiZA7JCLg8WcWbBTArLLxwMDva27OamsivlelK2bdOgZShj3TyT5te5hlcx9Cgikd8eFqJDpNQLtWYmgo4ovYNlkgMu72svIgLgDlnrcOqNJFWSKwpIgbKH2q33WOFwqN1XQK8cdfHaWSpVFbLRHFYSFbE4sGJ3aSWyvoF3L/qRy4gsdH30FUsTmhfczJ68MMkIQVYL40viC+Rxqi5YW0fbhOBOH9FQVuJFM9iFKkM+9adA5BEsHHLUyebZQR7CQkYdzonlaanWqOtTwbT83yDx+TmryTg8WxYwFZYx8OlI1p60huEuyQIkmaVUrmGik9sMr6A7SJIELjMrDO8G5LVD42xMywdtCBum/4LV3DQpmUIDCSEa437WMG+HSwDn7NHiRVxE92TEzYfBfWamGDSw078oekwSg8EwMxjZE50Ip9ljiefRlr45QwUnBL+TNc1Dl+/06V98HZghf3/DI+kE+zkGVceWAF45ZoYySFTkJFB4etpli3+m+rynDnkTSEOaxH4eVZMvBGvqeLucY9epwXYR9A124sJNykIqTpQh3+ZTihkgNY5FlcIo876z4617O5UVA54vCtuJxAxWIrpOm10Ms1eBSI6bs/+fd+12jk7BBN/vppsovTAoqlZwTfGKryxC+GJVZrmk/PfIduf88HBzA/+75L81S+5VGzWV9uGJBfyUe/iMrSjGrdxVu85pYNa4X4Fqfci+3r6gy65BgOD1bnCyINO+xjzBXNgpgDOwseNPylIuDV23yBkt+Wc490/+5xwlA5vAohhPdmGsynjixUtMNdvE= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(83380400001)(336012)(26005)(47076005)(86362001)(5660300002)(356005)(82310400005)(8936002)(36756003)(6666004)(7696005)(36860700001)(2616005)(186003)(2906002)(40460700003)(70586007)(7049001)(921005)(316002)(426003)(110136005)(8676002)(70206006)(508600001)(81166007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:25:50.6155 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a5da73c-aa77-4628-2116-08da1df0627a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB2647 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Tegra186 timer provides ten 29-bit timer counters and one 32-bit timestamp counter. The Tegra234 timer provides sixteen 29-bit timer counters and one 32-bit timestamp counter. Each NV timer selects its timing reference signal from the 1 MHz reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be programmed to generate one-shot, periodic, or watchdog interrupts. Signed-off-by: Kartik --- .../bindings/timer/nvidia,tegra186-timer.yaml | 116 ++++++++++++++++++ 1 file changed, 116 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra186= -timer.yaml diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.= yaml b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml new file mode 100644 index 000000000000..7841a68d19f3 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra186-timer.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra186 timer + +maintainers: + - Thierry Reding + +allOf: + - if: + properties: + compatible: + contains: + const: nvidia,tegra186-timer + then: + properties: + interrupts: + # Either a single combined interrupt or up to 14 individual inte= rrupts + minItems: 1 + maxItems: 10 + description: > + A list of 10 interrupts; one per each timer channels 0 through= 9. + + - if: + properties: + compatible: + contains: + const: nvidia,tegra234-timer + then: + properties: + interrupts: + # Either a single combined interrupt or up to 16 individual inte= rrupts + minItems: 1 + maxItems: 16 + description: > + A list of 16 interrupts; one per each timer channels 0 through= 15. + +properties: + compatible: + oneOf: + - const: nvidia,tegra186-timer + description: > + The Tegra186 timer provides ten 29-bit timer counters and one 32= -bit + timestamp counter. Each NV timer selects its timing reference si= gnal + from the 1 MHz reference generated by USEC, TSC or either clk_m = or + OSC. Each TMR can be programmed to generate one-shot, periodic, = or + watchdog interrupts. + - const: nvidia,tegra234-timer + description: > + The Tegra234 timer provides sixteen 29-bit timer counters and on= e 32-bit + timestamp counter. Each NV timer selects its timing reference si= gnal + from the 1 MHz reference generated by USEC, TSC or either clk_m = or + OSC. Each TMR can be programmed to generate one-shot, periodic, = or + watchdog interrupts. + + reg: + maxItems: 1 + + interrupts: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + timer@3010000 { + compatible =3D "nvidia,tegra186-timer"; + reg =3D <0x03010000 0x000e0000>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + status =3D "disabled"; + }; + + - | + #include + #include + + timer@2080000 { + compatible =3D "nvidia,tegra234-timer"; + reg =3D <0x02080000 0x00121000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status =3D "disabled"; + }; --=20 2.17.1 From nobody Mon May 11 04:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B80A0C43219 for ; Thu, 14 Apr 2022 08:26:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240901AbiDNI22 (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:25:56.5403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b5ed4de-f99f-4fef-a751-08da1df065f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT022.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3771 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thierry Reding Currently this only supports a single watchdog, which uses a timer in the background for countdown. Eventually the timers could be used for various time-keeping tasks, but by default the architected timer will already provide that functionality. Signed-off-by: Thierry Reding Signed-off-by: Kartik --- drivers/clocksource/Kconfig | 8 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-tegra186.c | 508 +++++++++++++++++++++++++++ 3 files changed, 517 insertions(+) create mode 100644 drivers/clocksource/timer-tegra186.c diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index fe3f05dfafd9..c68ecafc6ad1 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -150,6 +150,14 @@ config TEGRA_TIMER help Enables support for the Tegra driver. =20 +config TEGRA186_TIMER + tristate "NVIDIA Tegra186 timer driver" + depends on ARCH_TEGRA || COMPILE_TEST + depends on WATCHDOG && WATCHDOG_CORE + help + Enables support for the timers and watchdogs found on NVIDIA + Tegra186 and later SoCs. + config VT8500_TIMER bool "VT8500 timer driver" if COMPILE_TEST depends on HAS_IOMEM diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 833cfb7a96c1..a917811443d1 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_SUN4I_TIMER) +=3D timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) +=3D timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) +=3D timer-meson6.o obj-$(CONFIG_TEGRA_TIMER) +=3D timer-tegra.o +obj-$(CONFIG_TEGRA186_TIMER) +=3D timer-tegra186.o obj-$(CONFIG_VT8500_TIMER) +=3D timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) +=3D timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) +=3D bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/tim= er-tegra186.c new file mode 100644 index 000000000000..4515517c87a5 --- /dev/null +++ b/drivers/clocksource/timer-tegra186.c @@ -0,0 +1,508 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* shared registers */ +#define TKETSC0 0x000 +#define TKETSC1 0x004 +#define TKEUSEC 0x008 +#define TKEOSC 0x00c + +#define TKEIE(x) (0x100 + ((x) * 4)) +#define TKEIE_WDT_MASK(x, y) ((y) << (16 + 4 * (x))) + +/* timer registers */ +#define TMRCR 0x000 +#define TMRCR_ENABLE BIT(31) +#define TMRCR_PERIODIC BIT(30) +#define TMRCR_PTV(x) ((x) & 0x0fffffff) + +#define TMRSR 0x004 +#define TMRSR_INTR_CLR BIT(30) + +#define TMRCSSR 0x008 +#define TMRCSSR_SRC_USEC (0 << 0) + +/* watchdog registers */ +#define WDTCR 0x000 +#define WDTCR_SYSTEM_POR_RESET_ENABLE BIT(16) +#define WDTCR_SYSTEM_DEBUG_RESET_ENABLE BIT(15) +#define WDTCR_REMOTE_INT_ENABLE BIT(14) +#define WDTCR_LOCAL_FIQ_ENABLE BIT(13) +#define WDTCR_LOCAL_INT_ENABLE BIT(12) +#define WDTCR_PERIOD_MASK (0xff << 4) +#define WDTCR_PERIOD(x) (((x) & 0xff) << 4) +#define WDTCR_TIMER_SOURCE_MASK 0xf +#define WDTCR_TIMER_SOURCE(x) ((x) & 0xf) + +#define WDTCMDR 0x008 +#define WDTCMDR_DISABLE_COUNTER BIT(1) +#define WDTCMDR_START_COUNTER BIT(0) + +#define WDTUR 0x00c +#define WDTUR_UNLOCK_PATTERN 0x0000c45a + +struct tegra186_timer_soc { + unsigned int num_timers; + unsigned int num_wdts; +}; + +struct tegra186_tmr { + struct tegra186_timer *parent; + void __iomem *regs; + unsigned int index; + unsigned int hwirq; +}; + +struct tegra186_wdt { + struct watchdog_device base; + + void __iomem *regs; + unsigned int index; + bool locked; + + struct tegra186_tmr *tmr; +}; + +static inline struct tegra186_wdt *to_tegra186_wdt(struct watchdog_device = *wdd) +{ + return container_of(wdd, struct tegra186_wdt, base); +} + +struct tegra186_timer { + const struct tegra186_timer_soc *soc; + struct device *dev; + void __iomem *regs; + + struct tegra186_wdt *wdt; + struct clocksource usec; + struct clocksource tsc; + struct clocksource osc; +}; + +static void tmr_writel(struct tegra186_tmr *tmr, u32 value, unsigned int o= ffset) +{ + writel_relaxed(value, tmr->regs + offset); +} + +static void wdt_writel(struct tegra186_wdt *wdt, u32 value, unsigned int o= ffset) +{ + writel_relaxed(value, wdt->regs + offset); +} + +static u32 wdt_readl(struct tegra186_wdt *wdt, unsigned int offset) +{ + return readl_relaxed(wdt->regs + offset); +} + +static struct tegra186_tmr *tegra186_tmr_create(struct tegra186_timer *teg= ra, + unsigned int index) +{ + unsigned int offset =3D 0x10000 + index * 0x10000; + struct tegra186_tmr *tmr; + + tmr =3D devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); + if (!tmr) + return ERR_PTR(-ENOMEM); + + tmr->parent =3D tegra; + tmr->regs =3D tegra->regs + offset; + tmr->index =3D index; + tmr->hwirq =3D 0; + + return tmr; +} + +static const struct watchdog_info tegra186_wdt_info =3D { + .options =3D WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, + .identity =3D "NVIDIA Tegra186 WDT", +}; + +static void tegra186_wdt_disable(struct tegra186_wdt *wdt) +{ + /* unlock and disable the watchdog */ + wdt_writel(wdt, WDTUR_UNLOCK_PATTERN, WDTUR); + wdt_writel(wdt, WDTCMDR_DISABLE_COUNTER, WDTCMDR); + + /* disable timer */ + tmr_writel(wdt->tmr, 0, TMRCR); +} + +static void tegra186_wdt_enable(struct tegra186_wdt *wdt) +{ + struct tegra186_timer *tegra =3D wdt->tmr->parent; + u32 value; + + /* unmask hardware IRQ, this may have been lost across powergate */ + value =3D TKEIE_WDT_MASK(wdt->index, 1); + writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); + + /* clear interrupt */ + tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR); + + /* select microsecond source */ + tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); + + /* configure timer (system reset happens on the fifth expiration) */ + value =3D TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) | + TMRCR_PERIODIC | TMRCR_ENABLE; + tmr_writel(wdt->tmr, value, TMRCR); + + if (!wdt->locked) { + value =3D wdt_readl(wdt, WDTCR); + + /* select the proper timer source */ + value &=3D ~WDTCR_TIMER_SOURCE_MASK; + value |=3D WDTCR_TIMER_SOURCE(wdt->tmr->index); + + /* single timer period since that's already configured */ + value &=3D ~WDTCR_PERIOD_MASK; + value |=3D WDTCR_PERIOD(1); + + /* enable local interrupt for WDT petting */ + value |=3D WDTCR_LOCAL_INT_ENABLE; + + /* enable local FIQ and remote interrupt for debug dump */ + if (0) + value |=3D WDTCR_REMOTE_INT_ENABLE | + WDTCR_LOCAL_FIQ_ENABLE; + + /* enable system debug reset (doesn't properly reboot) */ + if (0) + value |=3D WDTCR_SYSTEM_DEBUG_RESET_ENABLE; + + /* enable system POR reset */ + value |=3D WDTCR_SYSTEM_POR_RESET_ENABLE; + + wdt_writel(wdt, value, WDTCR); + } + + wdt_writel(wdt, WDTCMDR_START_COUNTER, WDTCMDR); +} + +static int tegra186_wdt_start(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); + + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_stop(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + + return 0; +} + +static int tegra186_wdt_ping(struct watchdog_device *wdd) +{ + struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); + + tegra186_wdt_disable(wdt); + tegra186_wdt_enable(wdt); + + return 0; +} + +static int tegra186_wdt_set_timeout(struct watchdog_device *wdd, + unsigned int timeout) +{ + struct tegra186_wdt *wdt =3D to_tegra186_wdt(wdd); + + if (watchdog_active(&wdt->base)) + tegra186_wdt_disable(wdt); + + wdt->base.timeout =3D timeout; + + if (watchdog_active(&wdt->base)) + tegra186_wdt_enable(wdt); + + return 0; +} + +static const struct watchdog_ops tegra186_wdt_ops =3D { + .owner =3D THIS_MODULE, + .start =3D tegra186_wdt_start, + .stop =3D tegra186_wdt_stop, + .ping =3D tegra186_wdt_ping, + .set_timeout =3D tegra186_wdt_set_timeout, +}; + +static struct tegra186_wdt *tegra186_wdt_create(struct tegra186_timer *teg= ra, + unsigned int index) +{ + unsigned int offset =3D 0x10000, source; + struct tegra186_wdt *wdt; + u32 value; + int err; + + offset +=3D tegra->soc->num_timers * 0x10000 + index * 0x10000; + + wdt =3D devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); + if (!wdt) + return ERR_PTR(-ENOMEM); + + wdt->regs =3D tegra->regs + offset; + wdt->index =3D index; + + /* read the watchdog configuration since it might be locked down */ + value =3D wdt_readl(wdt, WDTCR); + + if (value & WDTCR_LOCAL_INT_ENABLE) + wdt->locked =3D true; + + source =3D value & WDTCR_TIMER_SOURCE_MASK; + + wdt->tmr =3D tegra186_tmr_create(tegra, source); + if (IS_ERR(wdt->tmr)) + return ERR_CAST(wdt->tmr); + + wdt->base.info =3D &tegra186_wdt_info; + wdt->base.ops =3D &tegra186_wdt_ops; + wdt->base.min_timeout =3D 1; + wdt->base.max_timeout =3D 255; + wdt->base.parent =3D tegra->dev; + + err =3D watchdog_init_timeout(&wdt->base, 5, tegra->dev); + if (err < 0) { + dev_err(tegra->dev, "failed to initialize timeout: %d\n", err); + return ERR_PTR(err); + } + + err =3D devm_watchdog_register_device(tegra->dev, &wdt->base); + if (err < 0) { + dev_err(tegra->dev, "failed to register WDT: %d\n", err); + return ERR_PTR(err); + } + + return wdt; +} + +static u64 tegra186_timer_tsc_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra =3D container_of(cs, struct tegra186_timer, + tsc); + u32 hi, lo, ss; + + hi =3D readl_relaxed(tegra->regs + TKETSC1); + + /* + * The 56-bit value of the TSC is spread across two registers that are + * not synchronized. In order to read them atomically, ensure that the + * high 24 bits match before and after reading the low 32 bits. + */ + do { + /* snapshot the high 24 bits */ + ss =3D hi; + + lo =3D readl_relaxed(tegra->regs + TKETSC0); + hi =3D readl_relaxed(tegra->regs + TKETSC1); + } while (hi !=3D ss); + + return (u64)hi << 32 | lo; +} + +static int tegra186_timer_tsc_init(struct tegra186_timer *tegra) +{ + tegra->tsc.name =3D "tsc"; + tegra->tsc.rating =3D 300; + tegra->tsc.read =3D tegra186_timer_tsc_read; + tegra->tsc.mask =3D CLOCKSOURCE_MASK(56); + tegra->tsc.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->tsc, 31250000); +} + +static u64 tegra186_timer_osc_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra =3D container_of(cs, struct tegra186_timer, + osc); + + return readl_relaxed(tegra->regs + TKEOSC); +} + +static int tegra186_timer_osc_init(struct tegra186_timer *tegra) +{ + tegra->osc.name =3D "osc"; + tegra->osc.rating =3D 300; + tegra->osc.read =3D tegra186_timer_osc_read; + tegra->osc.mask =3D CLOCKSOURCE_MASK(32); + tegra->osc.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->osc, 38400000); +} + +static u64 tegra186_timer_usec_read(struct clocksource *cs) +{ + struct tegra186_timer *tegra =3D container_of(cs, struct tegra186_timer, + usec); + + return readl_relaxed(tegra->regs + TKEUSEC); +} + +static int tegra186_timer_usec_init(struct tegra186_timer *tegra) +{ + tegra->usec.name =3D "usec"; + tegra->usec.rating =3D 300; + tegra->usec.read =3D tegra186_timer_usec_read; + tegra->usec.mask =3D CLOCKSOURCE_MASK(32); + tegra->usec.flags =3D CLOCK_SOURCE_IS_CONTINUOUS; + + return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); +} + +static irqreturn_t tegra186_timer_irq(int irq, void *data) +{ + struct tegra186_timer *tegra =3D data; + + if (watchdog_active(&tegra->wdt->base)) { + tegra186_wdt_disable(tegra->wdt); + tegra186_wdt_enable(tegra->wdt); + } + + return IRQ_HANDLED; +} + +static int tegra186_timer_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct tegra186_timer *tegra; + unsigned int irq; + int err; + + tegra =3D devm_kzalloc(dev, sizeof(*tegra), GFP_KERNEL); + if (!tegra) + return -ENOMEM; + + tegra->soc =3D of_device_get_match_data(dev); + dev_set_drvdata(dev, tegra); + tegra->dev =3D dev; + + tegra->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tegra->regs)) + return PTR_ERR(tegra->regs); + + err =3D platform_get_irq(pdev, 0); + if (err < 0) + return err; + + irq =3D err; + + /* create a watchdog using a preconfigured timer */ + tegra->wdt =3D tegra186_wdt_create(tegra, 0); + if (IS_ERR(tegra->wdt)) { + err =3D PTR_ERR(tegra->wdt); + dev_err(dev, "failed to create WDT: %d\n", err); + return err; + } + + err =3D tegra186_timer_tsc_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register TSC counter: %d\n", err); + return err; + } + + err =3D tegra186_timer_osc_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register OSC counter: %d\n", err); + goto unregister_tsc; + } + + err =3D tegra186_timer_usec_init(tegra); + if (err < 0) { + dev_err(dev, "failed to register USEC counter: %d\n", err); + goto unregister_osc; + } + + err =3D devm_request_irq(dev, irq, tegra186_timer_irq, 0, + "tegra186-timer", tegra); + if (err < 0) { + dev_err(dev, "failed to request IRQ#%u: %d\n", irq, err); + goto unregister_usec; + } + + return 0; + +unregister_usec: + clocksource_unregister(&tegra->usec); +unregister_osc: + clocksource_unregister(&tegra->osc); +unregister_tsc: + clocksource_unregister(&tegra->tsc); + return err; +} + +static int tegra186_timer_remove(struct platform_device *pdev) +{ + struct tegra186_timer *tegra =3D platform_get_drvdata(pdev); + + clocksource_unregister(&tegra->usec); + clocksource_unregister(&tegra->osc); + clocksource_unregister(&tegra->tsc); + + return 0; +} + +static int __maybe_unused tegra186_timer_suspend(struct device *dev) +{ + struct tegra186_timer *tegra =3D dev_get_drvdata(dev); + + if (watchdog_active(&tegra->wdt->base)) + tegra186_wdt_disable(tegra->wdt); + + return 0; +} + +static int __maybe_unused tegra186_timer_resume(struct device *dev) +{ + struct tegra186_timer *tegra =3D dev_get_drvdata(dev); + + if (watchdog_active(&tegra->wdt->base)) + tegra186_wdt_enable(tegra->wdt); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(tegra186_timer_pm_ops, tegra186_timer_suspend, + tegra186_timer_resume); + +static const struct tegra186_timer_soc tegra186_timer =3D { + .num_timers =3D 10, + .num_wdts =3D 3, +}; + +static const struct of_device_id tegra186_timer_of_match[] =3D { + { .compatible =3D "nvidia,tegra186-timer", .data =3D &tegra186_timer }, + { } +}; +MODULE_DEVICE_TABLE(of, tegra186_timer_of_match); + +static struct platform_driver tegra186_wdt_driver =3D { + .driver =3D { + .name =3D "tegra186-timer", + .pm =3D &tegra186_timer_pm_ops, + .of_match_table =3D tegra186_timer_of_match, + }, + .probe =3D tegra186_timer_probe, + .remove =3D tegra186_timer_remove, +}; +module_platform_driver(tegra186_wdt_driver); + +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra186 timers driver"); +MODULE_LICENSE("GPL v2"); --=20 2.17.1 From nobody Mon May 11 04:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1477C433EF for ; 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Thu, 14 Apr 2022 01:25:54 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 3/6] clocksource/drivers/timer-tegra186: Add support for Tegra234 SoC Date: Thu, 14 Apr 2022 13:55:35 +0530 Message-ID: <1649924738-17990-4-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7790612a-87b4-4025-d868-08da1df06841 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0234:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gojVAIOsJ3XSdOfo4WMQpaI+BaeEggxwEE3D7CDXagYZTLDQvpn863uJ9Sjh+5nq/Waujb73PlQ0hI38FECXlrh2BFLNHSOQudRYJ6HX7duUbV59SEqMzPC+V5F7r5ZJaQGkIdLxsSnpQkqcFpbihpzpnd6B/ut5c6dH2zQGfNeFqviXkIw8auxttt5amqx36hDjIWpUtrXNcvDJ8bxX7ZSsaUKuSCHSPDsJ70Vh7rm6oXmB+N7oZMsFiKcMLmSZryqa6GaTUt69lSN+FIbAxbwQtvt8zmjXIGAESOz/yHkTg4ioLs8e6mbanOqdVznj2ZpzTwCjI78GdOxg8aOKhiEEsD+L+w0493SWCbRTJaOnMmP0QsrantQzmK2VleKOwCDWtpADgp3bRb6oIGHf2fwCTIiTFMGoBQaiTUgp18m9nUgZXZSA0SIT3RWRarCO8QvMbYJDUnT669RVp40nzyeJk6ryrhFBBTCgRK2RdhhjAUV4f8mMfIIhOl56taOIjuN2ZeSCJKEBD6LlhB7y4R0FnqtWYo7pebfRfT2dAx2n1sX/YgJD1ROE8WdbrZn1oBWu13aUlyqCE+pSqu7NSupEa7iLLpFmyI2ierT4v6kZ6oLQNHIPHRFgw6FWd6cVILpQrdsu9WtLq4ckx1PkSvwXRRU1/pHg1tbTYfilmhK10iJ5RTLUOVCGHY+9jfFU8l4J5vM3wrUMUZl5KT+tj8g9l0KahSnReeqsmxy6Ii8= X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(8676002)(2906002)(316002)(47076005)(110136005)(921005)(4744005)(70586007)(70206006)(82310400005)(8936002)(508600001)(2616005)(40460700003)(7049001)(36756003)(5660300002)(36860700001)(86362001)(7696005)(81166007)(83380400001)(336012)(6666004)(426003)(186003)(26005)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:26:00.3598 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7790612a-87b4-4025-d868-08da1df06841 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0234 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The timer IP block present on Tegra234 SoC supports watchdog timer functionality that can be used to recover from system hangs. The watchdog timer uses a timer in the background for countdown. Signed-off-by: Kartik --- drivers/clocksource/timer-tegra186.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/tim= er-tegra186.c index 4515517c87a5..ea742889ee06 100644 --- a/drivers/clocksource/timer-tegra186.c +++ b/drivers/clocksource/timer-tegra186.c @@ -486,8 +486,14 @@ static const struct tegra186_timer_soc tegra186_timer = =3D { .num_wdts =3D 3, }; =20 +static const struct tegra186_timer_soc tegra234_timer =3D { + .num_timers =3D 16, + .num_wdts =3D 3, +}; + static const struct of_device_id tegra186_timer_of_match[] =3D { { .compatible =3D "nvidia,tegra186-timer", .data =3D &tegra186_timer }, + { .compatible =3D "nvidia,tegra234-timer", .data =3D &tegra234_timer }, { } }; MODULE_DEVICE_TABLE(of, tegra186_timer_of_match); --=20 2.17.1 From nobody Mon May 11 04:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3CCDC433EF for ; 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Thu, 14 Apr 2022 01:25:59 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 4/6] arm64: tegra: Enable native timers on Tegra186 Date: Thu, 14 Apr 2022 13:55:36 +0530 Message-ID: <1649924738-17990-5-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 931f0d7f-1661-412f-3f7a-08da1df06baa X-MS-TrafficTypeDiagnostic: DM5PR12MB1388:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Cfx18GjQ281xcXHC+1Pw3hEUpfcibJVkigIAszzmhrySZZQWZUxKZrktdm/ig/5a7Gj4znQTxzh7LDmgFuSHhO57IaDTnfPq0gbFUN7lcJCWv5rbGZI07Mgh1qRNXReKfNAGp9pwHH6uSC6YYp18jkrcQb1A1HfhR8kq7MsozIaku7ACRjCB3Vy8OXw3+S2cdGS6Adb5lyYmRBbUegnNjf+xsw6MY1bj71z/UR/gqYhc3fH40JSfnFX4BUSWb8QtDQHQfDCuoyKb7Ak7q8nY1RfBbjq1Bcieyy1MQmeTTHMLXaz1zTbwRGg31soSaAQuDwoEwXnetQ3ULASN8N+AQU5Q7JW+dwJSJ+aL0pGqbsm0ipB+0s0LYnFakcKPabOmxRSMRMEo3fs/Z2+hXjiZC8ye3BaC+qvSqstL4ZuolzudZUWjmuapV9AE5se6dNKITH4uu+T61CRqRkayan/Yd/N0Y8/0D5Xp+NbQgssPib2RZM6mlsC8ARgQUOozOKjZ2iHdsrWv7HxxmxXHx41XOMbHQhFYVvKOfrzg+WnhQZmUI7Tf1dnx/MfXA728ET1ZbY+UigitxAMNnfdvqu28Cl/kxf0d1ImnuZBXFKjDM5GSDVcnKbAnQ2BqH5E/kqZGHsMRWcWSV5ElTqYfI1xi2STCusfHpq5k7dlFdIDXV+sQJMa90gTZ5wE26KjGwjFNrqJGcodFiTw3ZaELjny4Rd3EBTuJmu9cabcPTe2DYw4= X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(81166007)(110136005)(4744005)(2616005)(83380400001)(8676002)(8936002)(40460700003)(6666004)(2906002)(316002)(7696005)(36860700001)(921005)(186003)(82310400005)(356005)(70206006)(70586007)(5660300002)(36756003)(508600001)(7049001)(26005)(336012)(86362001)(426003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:26:06.0772 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 931f0d7f-1661-412f-3f7a-08da1df06baa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1388 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the native timers on Tegra186 chips to allow using the watchdog functionality to recover from system hangs. Signed-off-by: Kartik --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts= /nvidia/tegra186.dtsi index e9b40f5d79ec..9969eaa39018 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -563,7 +563,7 @@ , , ; - status =3D "disabled"; + status =3D "okay"; }; =20 uarta: serial@3100000 { --=20 2.17.1 From nobody Mon May 11 04:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C77BC433F5 for ; Thu, 14 Apr 2022 08:26:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240924AbiDNI2t (ORCPT ); Thu, 14 Apr 2022 04:28:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240944AbiDNI2m (ORCPT ); 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Thu, 14 Apr 2022 08:26:09 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 14 Apr 2022 01:26:08 -0700 Received: from kkartik-desktop.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Thu, 14 Apr 2022 01:26:04 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 5/6] arm64: tegra: Enable native timers on Tegra194 Date: Thu, 14 Apr 2022 13:55:37 +0530 Message-ID: <1649924738-17990-6-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7ff0b61d-1f6d-4cff-caf9-08da1df06e3f X-MS-TrafficTypeDiagnostic: BY5PR12MB3812:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:26:10.4127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ff0b61d-1f6d-4cff-caf9-08da1df06e3f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3812 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thierry Reding The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra194. Signed-off-by: Thierry Reding Signed-off-by: Kartik --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 1d6be5774fac..fad2b1a634cb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -649,6 +649,22 @@ }; }; =20 + timer@3010000 { + compatible =3D "nvidia,tegra186-timer"; + reg =3D <0x03010000 0x000e0000>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + status =3D "okay"; + }; + uarta: serial@3100000 { compatible =3D "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg =3D <0x03100000 0x40>; --=20 2.17.1 From nobody Mon May 11 04:52:00 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81A53C433F5 for ; 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Thu, 14 Apr 2022 01:26:09 -0700 From: Kartik To: , , , , , , , , , , , , , , , , Subject: [PATCH 6/6] arm64: tegra: Enable native timers on Tegra234 Date: Thu, 14 Apr 2022 13:55:38 +0530 Message-ID: <1649924738-17990-7-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> References: <1649924738-17990-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1258e399-e489-4589-77b1-08da1df07137 X-MS-TrafficTypeDiagnostic: DM6PR12MB2697:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ezRIoqVitdA5MqNVUyAOxpCrMJDktqD9s9dQNlDdxrD6YqABqCl8DEI2r4dD0F7rfTDCCTPHvJIQyz7r4ZZuXiDIOzwVfpEnIzTZQRUsE6J9h6c79LcMw/+GWeF53ccTT7bu4ydbBKgJC4W8AhLbAk05TzgDoipqgzuCXLNg3B/dQI878QdPeDeWuy76XTDWJgg4D1dqsGQMVLPDMHd1yIjBUHoXvcGCZWZDARWs1GBu7wWBWLxpO0qYiBNrk7rcbq14BzNHiGD+zqkcZrZKiAZFzIhV2PVDzCo9Q2TRJsm2efVBGCmjK02eicC7DBH8ZF/xsYdSTq5DQUQK3kJtEvOWa7ZMxt+phKkO8X4+1EGWESsXqi+HgszCdchTglYIBFvFDQLNqmeUlhD5e3xNvFRB3Po/svKeG5kRSdNJjc7upBEarVra27VL/hznlzHOc6bv7jwl1SFVKto3xp8HDa8tSzHRD50X0rmffhQSH0bDd9hssMEmAjczHssLEPxy30ASn022mxX+z8ClxU4jtqWAXSgGWHBhBKv9H0bhlYPFzK+5JbGADfFA+tQpjhtJlyqLQiVnX63pxAtAkGAWLeaCo3wDzKiqH2xJTF6mNtT80oh5LemYxSWPM759bWwEL8GYzM5WD94VBuXxeEqPGVku83uIre+F9I5itEYx/3rR5kR3DFdnFX/iRFINuPXcCW/THQqorAjEmcWktLw/BIiJUTOjNlWSkcT1sccJJnU= X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(316002)(7696005)(47076005)(426003)(336012)(40460700003)(6666004)(82310400005)(86362001)(36756003)(83380400001)(5660300002)(26005)(186003)(8676002)(7049001)(508600001)(36860700001)(2616005)(70206006)(70586007)(356005)(2906002)(110136005)(81166007)(8936002)(921005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 08:26:15.3444 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1258e399-e489-4589-77b1-08da1df07137 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT031.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2697 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add and enable the device tree node on Tegra234. Signed-off-by: Kartik --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 8767dbe2d066..47e0500a3838 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -446,6 +446,28 @@ status =3D "okay"; }; =20 + timer@2080000 { + compatible =3D "nvidia,tegra234-timer"; + reg =3D <0x02080000 0x00121000>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + status =3D "okay"; + }; + gpio: gpio@2200000 { compatible =3D "nvidia,tegra234-gpio"; reg-names =3D "security", "gpio"; --=20 2.17.1