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Thu, 14 Apr 2022 00:36:01 -0700 From: Kartik To: , , , , , , , , Subject: [PATCH 1/3] mailbox: tegra-hsp: Add tegra_hsp_sm_ops Date: Thu, 14 Apr 2022 13:05:55 +0530 Message-ID: <1649921757-16919-2-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> References: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f70c816c-3f0c-4b16-26b5-08da1de96fbb X-MS-TrafficTypeDiagnostic: DM8PR12MB5414:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QfdSC4eiR68eGSyQkr4clBtr9/a5qgCWUNDkUguPDuSE/1r35WZXmU2aoBSFipvkfTMmKmmPKUWVFfpnZNBNG5Vsdwyv6+1T1hsGvw293JeI2rLWyIj4a501Jn9OWFXitrir7wSjTs04kwF46jSvsmyrnRCT1/wOe5np7XBvQj7ANmEHIZIKwrdgaHzHvDQtIDrhk7Lkv0EyqKo2t4qxq3eiRS7qISlih/YaTZ3sovSA1Ruu791W+IiP3nsbkALzjbPMLUTC29M/g/ki0LE4YRxwxU9eCxKonzwdFsnR7kcMZr0yuNPDsoprlwMCOLriB0671sXfobBCzt+rxXESjCieeHt3poLSoOzTmRbnVlYkjk3ZEj/ts/zQgiB9cc2Vx1w3FRhqanJn6LANh9N5S8qZWDupyyzErj4kSd2YP4sd2A5KPTuurx6wYBQ1ICu2sL8V2swZqPVL6m2H8Jryv18Ps2kgMcMb3Lk2ZqhnYCF/jNvirYgcVE+2RKhJm9cQk8BEoYLtZfhijb1i1oMamDZu2NqNQmcZc8Trh38y4MYRKpREOlaGR2XQtlEo1aieFFGnpN8ZsIxLCWG0qwWWYriKLxZCslcdMjJTQpLF47ygPrLt+Htqlonsajr3LA9ZWHnoVI2waM7F1u/WbuysYJ5f4Z4MbTtJO1Yo/73Kt2+g5qp2J+rNBpF8Z5cmmPPaO2G1l7qzLYoDgtfY6Bgagw== X-Forefront-Antispam-Report: CIP:12.22.5.236;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(36756003)(36860700001)(336012)(426003)(47076005)(186003)(26005)(82310400005)(7049001)(15650500001)(2616005)(2906002)(83380400001)(40460700003)(7696005)(6666004)(508600001)(316002)(5660300002)(8936002)(8676002)(81166007)(356005)(86362001)(70206006)(70586007)(110136005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 07:36:06.3905 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f70c816c-3f0c-4b16-26b5-08da1de96fbb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.236];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR12MB5414 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This patch introduces tegra_hsp_sm_ops to abstract send & receive API's for shared mailboxes. Signed-off-by: Kartik --- drivers/mailbox/tegra-hsp.c | 74 +++++++++++++++++++++++-------------- 1 file changed, 47 insertions(+), 27 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 78f7265039c6..af61ae43ab09 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -67,8 +67,14 @@ struct tegra_hsp_doorbell { unsigned int index; }; =20 +struct tegra_hsp_sm_ops { + void (*send)(struct tegra_hsp_channel *channel, void *data); + void (*recv)(struct tegra_hsp_channel *channel); +}; + struct tegra_hsp_mailbox { struct tegra_hsp_channel channel; + const struct tegra_hsp_sm_ops *ops; unsigned int index; bool producer; }; @@ -208,8 +214,7 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void *= data) { struct tegra_hsp *hsp =3D data; unsigned long bit, mask; - u32 status, value; - void *msg; + u32 status; =20 status =3D tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask; =20 @@ -245,25 +250,8 @@ static irqreturn_t tegra_hsp_shared_irq(int irq, void = *data) for_each_set_bit(bit, &mask, hsp->num_sm) { struct tegra_hsp_mailbox *mb =3D &hsp->mailboxes[bit]; =20 - if (!mb->producer) { - value =3D tegra_hsp_channel_readl(&mb->channel, - HSP_SM_SHRD_MBOX); - value &=3D ~HSP_SM_SHRD_MBOX_FULL; - msg =3D (void *)(unsigned long)value; - mbox_chan_received_data(mb->channel.chan, msg); - - /* - * Need to clear all bits here since some producers, - * such as TCU, depend on fields in the register - * getting cleared by the consumer. - * - * The mailbox API doesn't give the consumers a way - * of doing that explicitly, so we have to make sure - * we cover all possible cases. - */ - tegra_hsp_channel_writel(&mb->channel, 0x0, - HSP_SM_SHRD_MBOX); - } + if (!mb->producer) + mb->ops->recv(&mb->channel); } =20 return IRQ_HANDLED; @@ -372,21 +360,52 @@ static const struct mbox_chan_ops tegra_hsp_db_ops = =3D { .shutdown =3D tegra_hsp_doorbell_shutdown, }; =20 +static void tegra_hsp_sm_send32(struct tegra_hsp_channel *channel, void *d= ata) +{ + u32 value; + + /* copy data and mark mailbox full */ + value =3D (u32)(unsigned long)data; + value |=3D HSP_SM_SHRD_MBOX_FULL; + + tegra_hsp_channel_writel(channel, value, HSP_SM_SHRD_MBOX); +} + +static void tegra_hsp_sm_recv32(struct tegra_hsp_channel *channel) +{ + u32 value; + void *msg; + + value =3D tegra_hsp_channel_readl(channel, HSP_SM_SHRD_MBOX); + value &=3D ~HSP_SM_SHRD_MBOX_FULL; + msg =3D (void *)(unsigned long)value; + mbox_chan_received_data(channel->chan, msg); + + /* + * Need to clear all bits here since some producers, such as TCU, depend + * on fields in the register getting cleared by the consumer. + * + * The mailbox API doesn't give the consumers a way of doing that + * explicitly, so we have to make sure we cover all possible cases. + */ + tegra_hsp_channel_writel(channel, 0x0, HSP_SM_SHRD_MBOX); +} + +static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bit_ops =3D { + .send =3D tegra_hsp_sm_send32, + .recv =3D tegra_hsp_sm_recv32, +}; + static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) { struct tegra_hsp_mailbox *mb =3D chan->con_priv; struct tegra_hsp *hsp =3D mb->channel.hsp; unsigned long flags; - u32 value; =20 if (WARN_ON(!mb->producer)) return -EPERM; =20 - /* copy data and mark mailbox full */ - value =3D (u32)(unsigned long)data; - value |=3D HSP_SM_SHRD_MBOX_FULL; - - tegra_hsp_channel_writel(&mb->channel, value, HSP_SM_SHRD_MBOX); + mb->ops->send(&mb->channel, data); =20 /* enable EMPTY interrupt for the shared mailbox */ spin_lock_irqsave(&hsp->lock, flags); @@ -557,6 +576,7 @@ static struct mbox_chan *tegra_hsp_sm_xlate(struct mbox= _controller *mbox, return ERR_PTR(-ENODEV); =20 mb =3D &hsp->mailboxes[index]; + mb->ops =3D &tegra_hsp_sm_32bit_ops; =20 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) =3D=3D 0) mb->producer =3D false; --=20 2.17.1 From nobody Mon May 11 04:52:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E10EDC43217 for ; Thu, 14 Apr 2022 07:36:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240396AbiDNHif (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 07:36:07.6624 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3cbbeb57-269c-410e-13ed-08da1de97076 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3616 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra234 supports sending/receiving 32-bit and 128-bit data over a shared mailbox. Based on the data size to be used, clients need to specify the type of shared mailbox in the device tree. Add a macro for 128-bit shared mailbox. Mailbox clients can use this macro as a flag in device tree to enable 128-bit data support for a shared mailbox. Signed-off-by: Kartik Acked-by: Rob Herring --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 9 +++++++++ include/dt-bindings/mailbox/tegra186-hsp.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.= yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index 9f7a7296b57f..a3e87516d637 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -26,6 +26,15 @@ description: | second cell is used to identify the mailbox that the client is going to use. =20 + For shared mailboxes, the first cell composed of two fields: + - bits 15..8: + A bit mask of flags that further specifies the type of shared + mailbox to be used (based on the data size). If no flag is + specified then, 32-bit shared mailbox is used. + - bits 7..0: + Defines the type of the mailbox to be used. This field should be + TEGRA_HSP_MBOX_TYPE_SM for shared mailboxes. + For doorbells, the second cell specifies the index of the doorbell to use. =20 diff --git a/include/dt-bindings/mailbox/tegra186-hsp.h b/include/dt-bindin= gs/mailbox/tegra186-hsp.h index 3bdec7a84d35..b9ccae2aa9e2 100644 --- a/include/dt-bindings/mailbox/tegra186-hsp.h +++ b/include/dt-bindings/mailbox/tegra186-hsp.h @@ -15,6 +15,11 @@ #define TEGRA_HSP_MBOX_TYPE_SS 0x2 #define TEGRA_HSP_MBOX_TYPE_AS 0x3 =20 +/* + * These define the types of shared mailbox supported based on data size. + */ +#define TEGRA_HSP_MBOX_TYPE_SM_128BIT (1 << 8) + /* * These defines represent the bit associated with the given master ID in = the * doorbell registers. --=20 2.17.1 From nobody Mon May 11 04:52:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 684C4C433F5 for ; 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Thu, 14 Apr 2022 00:36:07 -0700 From: Kartik To: , , , , , , , , Subject: [PATCH 3/3] mailbox: tegra-hsp: Add 128-bit shared mailbox support Date: Thu, 14 Apr 2022 13:05:57 +0530 Message-ID: <1649921757-16919-4-git-send-email-kkartik@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> References: <1649921757-16919-1-git-send-email-kkartik@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 44143230-4a7e-4888-1c34-08da1de972b6 X-MS-TrafficTypeDiagnostic: DM5PR12MB4677:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: E6tGrtNBka+mD9zVsXfydLEZUhWKeUhWXMhtSZDmVBdJU+mdF4rLSQhvdn4NC7QaM9goAfqeSsXWrmanmQBfJ1jCH0+Sww45YTj0XudVWTkf8SJBW2jdcAbv/q6x4rgS4ngdkB2I+HEsUk6DQr4E6x19BGkT0vTmf5MMCWUzLQCALwd9o2XGLlVjswATW9w5yq+saiABP+wbYcIgQA1mgcGUs7EeZDgdtwkd91hzOUFous5J5iR1+aV9K2Av12VMc0YA0Iz+f9ZW/Wg8xj9w9w6birqZ+JvSHRO5hx2mgUBSqU11NvkPtHL5MkUZSp6hl0xS0ivj+8RpIkMH7wRJqYqXrtzVa9E1VKbj7vb33GSdAuI5J2qVK26qEryW4KrwxPNsInyYFVeLwN/xpRfGsQJul0Rpx9CLC/uDbqjITdFObzWZtCAft2Gg8HnDxS5DO6z5XyJdUy+/hNrufTvYv17N+lbW9vpZd79ZycPWbRVEtQWk/ulUNBaAu9UNtQjh3nAjOVHrbmfqK9UMvoMDqjXAQxPT0Oc1Cd8jHXw67dZIBy0WXv+NTqA8yzf+M8m4d8Dj56wFIAyfHLyEBNI86gV9sfihwEH22gdPR2GJpPaASj7DHi7KtYBqMLWXbxBio5En6LTNtPMOHNk9h+qA3dPBS8egCPHr/8OMWF0ebMhm0QWIAvTB1d1sNIexLSMUCpO5+Uuq+Jvqg0R7d+hvlQ== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(316002)(36860700001)(15650500001)(82310400005)(8936002)(2906002)(36756003)(110136005)(81166007)(7049001)(356005)(70586007)(5660300002)(70206006)(8676002)(40460700003)(86362001)(508600001)(6666004)(83380400001)(426003)(26005)(336012)(2616005)(7696005)(186003)(47076005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2022 07:36:11.4375 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44143230-4a7e-4888-1c34-08da1de972b6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB4677 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for 128-bit shared mailboxes found on Tegra234 chips. Signed-off-by: Kartik --- drivers/mailbox/tegra-hsp.c | 77 +++++++++++++++++++++++++++++++++++-- 1 file changed, 74 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index af61ae43ab09..f58448b10d90 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -46,10 +46,18 @@ #define HSP_SM_SHRD_MBOX_FULL_INT_IE 0x04 #define HSP_SM_SHRD_MBOX_EMPTY_INT_IE 0x08 =20 +#define HSP_SHRD_MBOX_TYPE1_TAG 0x40 +#define HSP_SHRD_MBOX_TYPE1_DATA0 0x48 +#define HSP_SHRD_MBOX_TYPE1_DATA1 0x4c +#define HSP_SHRD_MBOX_TYPE1_DATA2 0x50 +#define HSP_SHRD_MBOX_TYPE1_DATA3 0x54 + #define HSP_DB_CCPLEX 1 #define HSP_DB_BPMP 3 #define HSP_DB_MAX 7 =20 +#define HSP_MBOX_TYPE_MASK 0xff + struct tegra_hsp_channel; struct tegra_hsp; =20 @@ -88,6 +96,7 @@ struct tegra_hsp_db_map { struct tegra_hsp_soc { const struct tegra_hsp_db_map *map; bool has_per_mb_ie; + bool has_128_bit_mb; }; =20 struct tegra_hsp { @@ -396,6 +405,51 @@ static const struct tegra_hsp_sm_ops tegra_hsp_sm_32bi= t_ops =3D { .recv =3D tegra_hsp_sm_recv32, }; =20 +static void tegra_hsp_sm_send128(struct tegra_hsp_channel *channel, void *= data) +{ + u32 value[4]; + + memcpy(value, data, sizeof(value)); + + /* Copy data */ + tegra_hsp_channel_writel(channel, value[0], HSP_SHRD_MBOX_TYPE1_DATA0); + tegra_hsp_channel_writel(channel, value[1], HSP_SHRD_MBOX_TYPE1_DATA1); + tegra_hsp_channel_writel(channel, value[2], HSP_SHRD_MBOX_TYPE1_DATA2); + tegra_hsp_channel_writel(channel, value[3], HSP_SHRD_MBOX_TYPE1_DATA3); + + /* Update tag to mark mailbox full */ + tegra_hsp_channel_writel(channel, HSP_SM_SHRD_MBOX_FULL, + HSP_SHRD_MBOX_TYPE1_TAG); +} + +static void tegra_hsp_sm_recv128(struct tegra_hsp_channel *channel) +{ + u32 value[4]; + void *msg; + + value[0] =3D tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA0); + value[1] =3D tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA1); + value[2] =3D tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA2); + value[3] =3D tegra_hsp_channel_readl(channel, HSP_SHRD_MBOX_TYPE1_DATA3); + + msg =3D (void *)(unsigned long)value; + mbox_chan_received_data(channel->chan, msg); + + /* + * Clear data registers and tag. + */ + tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA0); + tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA1); + tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA2); + tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_DATA3); + tegra_hsp_channel_writel(channel, 0x0, HSP_SHRD_MBOX_TYPE1_TAG); +} + +static const struct tegra_hsp_sm_ops tegra_hsp_sm_128bit_ops =3D { + .send =3D tegra_hsp_sm_send128, + .recv =3D tegra_hsp_sm_recv128, +}; + static int tegra_hsp_mailbox_send_data(struct mbox_chan *chan, void *data) { struct tegra_hsp_mailbox *mb =3D chan->con_priv; @@ -571,12 +625,20 @@ static struct mbox_chan *tegra_hsp_sm_xlate(struct mb= ox_controller *mbox, =20 index =3D args->args[1] & TEGRA_HSP_SM_MASK; =20 - if (type !=3D TEGRA_HSP_MBOX_TYPE_SM || !hsp->shared_irqs || - index >=3D hsp->num_sm) + if ((type & HSP_MBOX_TYPE_MASK) !=3D TEGRA_HSP_MBOX_TYPE_SM || + !hsp->shared_irqs || index >=3D hsp->num_sm) return ERR_PTR(-ENODEV); =20 mb =3D &hsp->mailboxes[index]; - mb->ops =3D &tegra_hsp_sm_32bit_ops; + + if (type & TEGRA_HSP_MBOX_TYPE_SM_128BIT) { + if (!hsp->soc->has_128_bit_mb) + return ERR_PTR(-ENODEV); + + mb->ops =3D &tegra_hsp_sm_128bit_ops; + } else { + mb->ops =3D &tegra_hsp_sm_32bit_ops; + } =20 if ((args->args[1] & TEGRA_HSP_SM_FLAG_TX) =3D=3D 0) mb->producer =3D false; @@ -853,16 +915,25 @@ static const struct tegra_hsp_db_map tegra186_hsp_db_= map[] =3D { static const struct tegra_hsp_soc tegra186_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D false, + .has_128_bit_mb =3D false, }; =20 static const struct tegra_hsp_soc tegra194_hsp_soc =3D { .map =3D tegra186_hsp_db_map, .has_per_mb_ie =3D true, + .has_128_bit_mb =3D false, +}; + +static const struct tegra_hsp_soc tegra234_hsp_soc =3D { + .map =3D tegra186_hsp_db_map, + .has_per_mb_ie =3D false, + .has_128_bit_mb =3D true, }; =20 static const struct of_device_id tegra_hsp_match[] =3D { { .compatible =3D "nvidia,tegra186-hsp", .data =3D &tegra186_hsp_soc }, { .compatible =3D "nvidia,tegra194-hsp", .data =3D &tegra194_hsp_soc }, + { .compatible =3D "nvidia,tegra234-hsp", .data =3D &tegra234_hsp_soc }, { } }; =20 --=20 2.17.1