From nobody Mon May 11 06:18:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC629C433F5 for ; Tue, 12 Apr 2022 13:23:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347562AbiDLNZS (ORCPT ); Tue, 12 Apr 2022 09:25:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355716AbiDLNYV (ORCPT ); Tue, 12 Apr 2022 09:24:21 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8D1024F24; Tue, 12 Apr 2022 06:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649769318; x=1681305318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=DxS3ZyjzkyOPLu53HmEj7fHH/b4qI5+E/iryReh3D7M=; b=bwsL/hAZ/lV7LODzHjjtgtsEbttPITcCgYuOvUhVlL+ASRq2o3kbYlYa GV3D0B6eox8bOILG33hWMUqHGhaOziZYjV+Yk44ghY4bxeGx0EFMbr5c+ XFYqMB8sOuVOIZ15keRJ/5lAdiwlXmKrc1kFKWIREreD8RQXyADcZEDbj c=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 12 Apr 2022 06:15:18 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 06:15:18 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 06:15:17 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 06:15:13 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v8 1/2] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Tue, 12 Apr 2022 18:44:40 +0530 Message-ID: <1649769281-12458-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649769281-12458-1-git-send-email-quic_srivasam@quicinc.com> References: <1649769281-12458-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinmux nodes for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++= ++++ 2 files changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index ecbf2b8..1fc94b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -359,6 +359,20 @@ bias-disable; }; =20 +&mi2s1_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&mi2s1_ws { + drive-strength =3D <6>; +}; + &pm7325_gpios { key_vol_up_default: key-vol-up-default { pins =3D "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index f0b64be..6e6cfeda 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3522,6 +3522,46 @@ function =3D "edp_hot"; }; =20 + mi2s0_data0: mi2s0-data0 { + pins =3D "gpio98"; + function =3D "mi2s0_data0"; + }; + + mi2s0_data1: mi2s0-data1 { + pins =3D "gpio99"; + function =3D "mi2s0_data1"; + }; + + mi2s0_mclk: mi2s0-mclk { + pins =3D "gpio96"; + function =3D "pri_mi2s"; + }; + + mi2s0_sclk: mi2s0-sclk { + pins =3D "gpio97"; + function =3D "mi2s0_sck"; + }; + + mi2s0_ws: mi2s0-ws { + pins =3D "gpio100"; + function =3D "mi2s0_ws"; + }; + + mi2s1_data0: mi2s1-data0 { + pins =3D "gpio107"; + function =3D "mi2s1_data0"; + }; + + mi2s1_sclk: mi2s1-sclk { + pins =3D "gpio106"; + function =3D "mi2s1_sck"; + }; + + mi2s1_ws: mi2s1-ws { + pins =3D "gpio108"; + function =3D "mi2s1_ws"; + }; + pcie1_clkreq_n: pcie1-clkreq-n { pins =3D "gpio79"; function =3D "pcie1_clkreqn"; --=20 2.7.4 From nobody Mon May 11 06:18:53 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F241C4321E for ; Tue, 12 Apr 2022 13:23:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239485AbiDLNZf (ORCPT ); Tue, 12 Apr 2022 09:25:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355928AbiDLNYt (ORCPT ); Tue, 12 Apr 2022 09:24:49 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7043E2BB0D; Tue, 12 Apr 2022 06:15:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649769323; x=1681305323; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=e5rDwNyZ+Uqm84iaVDuX3yfceIEnyCM9hoJwRrjKywM=; b=MncWFDEBLQ7+tHDuWUnQz32krfMdx453qVkpxrW8ucklM8v5fTvFjSTn 9c5YHAllNHKAn7DODLBiFKsYCs+dC+fwGUUMJU+tPL7PWMya9Dx++mN0F xv7FUNB//8cKIfdocHx0ElcUqGgUD19DrmtvaUDqAEDNN0ypNii96t58Q U=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 12 Apr 2022 06:15:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2022 06:15:22 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 06:15:22 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 12 Apr 2022 06:15:17 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v8 2/2] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Date: Tue, 12 Apr 2022 18:44:41 +0530 Message-ID: <1649769281-12458-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649769281-12458-1-git-send-email-quic_srivasam@quicinc.com> References: <1649769281-12458-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LPASS LPI pinctrl node required for Audio functionality on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 84 ++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++++++++++++++++++++= ++++ 2 files changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 1fc94b5..53e5c91 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -238,6 +238,90 @@ modem-init; }; =20 +&dmic01 { + clk { + drive-strength =3D <8>; + }; +}; + +&dmic01_sleep { + clk { + drive-strength =3D <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&dmic23 { + clk { + drive-strength =3D <8>; + }; +}; + +&dmic23_sleep { + clk { + drive-strength =3D <2>; + bias-disable; + }; + + data { + pull-down; + }; +}; + +&rx_swr { + clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; +}; + +&rx_swr_sleep { + clk { + drive-strength =3D <2>; + bias-pull-down; + }; + + data { + drive-strength =3D <2>; + bias-pull-down; + }; +}; + +&tx_swr { + clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + slew-rate =3D <1>; + bias-bus-hold; + }; +}; + +&tx_swr_sleep { + clk { + drive-strength =3D <2>; + bias-pull-down; + }; + + data { + bias-bus-hold; + }; +}; + &pcie1 { status =3D "okay"; perst-gpio =3D <&tlmm 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 6e6cfeda..91f78bb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1987,6 +1987,113 @@ qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sc7280-lpass-lpi-pinctrl"; + reg =3D <0 0x033c0000 0x0 0x20000>, + <0 0x03550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + #clock-cells =3D <1>; + + dmic01: dmic01 { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + }; + + dmic01_sleep: dmic01-sleep { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + }; + + dmic23: dmic23 { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + }; + + dmic23_sleep: dmic23-sleep { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + }; + + rx_swr: rx-swr { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + }; + + rx_swr_sleep: rx-swr-sleep { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + }; + + tx_swr: tx-swr { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + }; + + tx_swr_sleep: tx-swr-sleep { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + }; + }; + gpu: gpu@3d00000 { compatible =3D "qcom,adreno-635.0", "qcom,adreno"; reg =3D <0 0x03d00000 0 0x40000>, --=20 2.7.4