From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F274DC433F5 for ; Mon, 11 Apr 2022 09:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244087AbiDKJzR (ORCPT ); Mon, 11 Apr 2022 05:55:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345009AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3406B41639; Mon, 11 Apr 2022 02:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670649; x=1681206649; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+xbfqnRznVX2Jfz5mYMD6PsZmXfJrHkCWmv6tLKMjMg=; b=TnoCjulOL4A/06iw1LWqy6JgFJQQwopxJ0wvmP0mWhWMPlpjCdARqZ7k hclVvl/DgBlGjodIZav893/77Znwq8DrBtH/H6kEEVE+9d2YynnzmrE0y 61w/JuP6kONeLEcsCA1SVE+iRoJHwwL4NJTdsTBA41nK9QEntG9vuPZwR s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:47 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:24 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id C4C0D3AA3; Mon, 11 Apr 2022 15:20:23 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Date: Mon, 11 Apr 2022 15:20:09 +0530 Message-Id: <1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add reserved memory nodes to the SDX65 dtsi as defined by the memory map. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++++++= ++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-= sdx65-mtp.dts index ad99f56..79dc31a 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -23,6 +23,27 @@ stdout-path =3D "serial0:115200n8"; }; =20 + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + mpss_dsm: memory@8c400000 { + no-map; + reg =3D <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg =3D <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg =3D <0x90800000 0x10000000>; + }; + }; + vph_pwr: vph-pwr-regulator { compatible =3D "regulator-fixed"; regulator-name =3D "vph_pwr"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index 7e2697f..dcc94c2 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -61,11 +61,56 @@ #size-cells =3D <1>; ranges; =20 + tz_heap_mem: memory@8fcad000 { + no-map; + reg =3D <0x8fcad000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg =3D <0x8fcfd000 0x1000>; + }; + + hyp_mem: memory@8fd00000 { + no-map; + reg =3D <0x8fd00000 0x80000>; + }; + + access_control_mem: memory@8fd80000 { + no-map; + reg =3D <0x8fd80000 0x80000>; + }; + + aop_mem: memory@8fe00000 { + no-map; + reg =3D <0x8fe00000 0x20000>; + }; + + smem_mem: memory@8fe20000 { + no-map; + reg =3D <0x8fe20000 0xc0000>; + }; + cmd_db: reserved-memory@8fee0000 { compatible =3D "qcom,cmd-db"; reg =3D <0x8fee0000 0x20000>; no-map; }; + + tz_mem: memory@8ff00000 { + no-map; + reg =3D <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg =3D <0x90000000 0x500000>; + }; + + llcc_tcm_mem: memory@15800000 { + no-map; + reg =3D <0x15800000 0x800000>; + }; }; =20 soc: soc { --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6909C433EF for ; Mon, 11 Apr 2022 09:52:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344807AbiDKJyZ (ORCPT ); Mon, 11 Apr 2022 05:54:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345019AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2ABD41990; Mon, 11 Apr 2022 02:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670653; x=1681206653; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=6DuQXv0swliwllJVJ21CJYS4OSZ+0fLxCJMDIFN2Mw8=; b=orKdWyeehGdutqu3jad+u985Sygii4WmnSAuvZMFF0b8H9hfvGXyaTd2 gfU/y25gAkd0sMjDCmABqI0HAaGAL/L9AWD8RHnFLIFNQ13HmwzsLgq2w cBOkyBH6WWrqJA3EoE6Bh/3Hl6b/m9HpB3cOPD/RjbipK0rib4CpIX89z k=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:25 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 19D623AA5; Mon, 11 Apr 2022 15:20:24 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Date: Mon, 11 Apr 2022 15:20:10 +0530 Message-Id: <1649670615-21268-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Document= ation/devicetree/bindings/mmc/sdhci-msm.txt index 6216ed7..e7dec8a 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -25,6 +25,7 @@ Required properties: "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" NOTE that some old device tree files may be floating around that only have the string "qcom,sdhci-msm-v4" without the SoC compatible string --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2821EC433EF for ; Mon, 11 Apr 2022 09:52:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344822AbiDKJyo (ORCPT ); Mon, 11 Apr 2022 05:54:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345008AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 719434162A; Mon, 11 Apr 2022 02:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670645; x=1681206645; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=lKgU7DGnnJO1363k0XRN8KK92ZB2lTy71WHh/n83z8M=; b=qnA+dPOAa2OLrGRSqzTkPkNcZyV7i1cRdwRjOQ0BH4iGH56sTuSaD8sS dKs3heB5rATySoOJZcyZL1Jgoy+5IOixT8uvchk5zDvqKyO1G+WIag42D C4AjdEOCvxdbkuBLIYu25LGgyx8vJyIQ1TFC0O1FF/QMe9Lvz5YdjMKX8 s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:45 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:43 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:25 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 6C8093AB3; Mon, 11 Apr 2022 15:20:24 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 3/7] ARM: dts: qcom: sdx65: Add support for SDHCI controller Date: Mon, 11 Apr 2022 15:20:11 +0530 Message-Id: <1649670615-21268-4-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add devicetree support for SDHCI controller found in Qualcomm SDX65 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index dcc94c2..77bca58 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -137,6 +137,19 @@ status =3D "disabled"; }; =20 + sdhc_1: sdhci@8804000 { + compatible =3D "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x08804000 0x1000>; + reg-names =3D "hc_mem"; + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + clocks =3D <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names =3D "core", "iface"; + status =3D "disabled"; + }; + spmi_bus: qcom,spmi@c440000 { compatible =3D "qcom,spmi-pmic-arb"; reg =3D <0xc440000 0xd00>, --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8552C433EF for ; Mon, 11 Apr 2022 09:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241501AbiDKJyW (ORCPT ); Mon, 11 Apr 2022 05:54:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345020AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6195541992; Mon, 11 Apr 2022 02:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670653; x=1681206653; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4sArmmPqK1fpsAra+ctcw1Mg8/kPFO/JwQ40cELNy00=; b=jNY70JwcHlYuriIrgeCYlJM8++mvOKSW1mAOUzMOcGSlWpNG1KMo07ph xP+0IJmnZrHWnlGbAPC4SaBJaAsqS2f7Ttex2OMCjy9N+MDZd71iLw/hz TGZUPlbZhONPQi+GQYCCybXPAYxK7jc4m2eZKNhZOVDp0U1783nOOjW5t E=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:53 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:25 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id CAC7D3AB8; Mon, 11 Apr 2022 15:20:24 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Date: Mon, 11 Apr 2022 15:20:12 +0530 Message-Id: <1649670615-21268-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add devicetree binding for Qualcomm SDX65 SMMU. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index da5381c..1f99bff 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -39,6 +39,7 @@ properties: - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0670C433F5 for ; Mon, 11 Apr 2022 09:53:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344855AbiDKJzK (ORCPT ); Mon, 11 Apr 2022 05:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345010AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F41E3CA4D; Mon, 11 Apr 2022 02:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670651; x=1681206651; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=xzRH/Ivs+0i07Ts6lK6bing4ar3/peg9rJMOQp2xa08=; b=R50NF2sL+jLIELWoKUDwn1lyMhaF+8MDZdP8AdISwjSRDlahhPRlh/tP RTpFwGxFyuIDPY6D4cCMbe3JQCe/aDDl2PAJocmd55rD4nFk3sa8JEvqy KU5CIQcA3l4cclqa9y25bwSi/66Y7TAZUgyxtftX1bMVJCYUJYfuq2U9e g=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:26 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 32E343AB9; Mon, 11 Apr 2022 15:20:25 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Date: Mon, 11 Apr 2022 15:20:13 +0530 Message-Id: <1649670615-21268-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add a node for the ARM SMMU found in the SDX65. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index 77bca58..f50a8a4 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -190,6 +190,46 @@ interrupt-controller; }; =20 + apps_smmu: iommu@15000000 { + compatible =3D "qcom,sdx65-smmu-500", "arm,mmu-500"; + reg =3D <0x15000000 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17800000 { compatible =3D "qcom,msm-qgic2"; interrupt-controller; --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0F9AC433F5 for ; Mon, 11 Apr 2022 09:52:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344800AbiDKJyd (ORCPT ); Mon, 11 Apr 2022 05:54:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345016AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD4C94198E; Mon, 11 Apr 2022 02:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670652; x=1681206652; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=i/ljBsm2MD9nNiXlMhM5SAGKdRLtBR+dGXw5lsuABgE=; b=w3U0bygSIeN40QIFOXYESB0GQx5A6VhfrdFu+0bLD0oAKgULgH0XnyKR ysH6avxAbjaBZ9L/bcOtub1Sbqc8ZWuwhpKtSnVstvcWKewyfeZOD8HJV /4MpLq2VGU6izE2W7JnMmwm+Kzy6j73WILD01seUMbvJh+X9Y6i8Jw2Xh g=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:27 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 82DCC3A9B; Mon, 11 Apr 2022 15:20:26 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Date: Mon, 11 Apr 2022 15:20:14 +0530 Message-Id: <1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index f50a8a4..210e55c 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -137,6 +137,12 @@ status =3D "disabled"; }; =20 + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x01f40000 0x40000>; + #hwlock-cells =3D <1>; + }; + sdhc_1: sdhci@8804000 { compatible =3D "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0x08804000 0x1000>; --=20 2.7.4 From nobody Mon May 11 07:48:14 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA0D3C433F5 for ; Mon, 11 Apr 2022 09:52:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344852AbiDKJyz (ORCPT ); Mon, 11 Apr 2022 05:54:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345007AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 346864162C; Mon, 11 Apr 2022 02:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670647; x=1681206647; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=pz9Q9tfygcswvzxpNlt2xnEXl7RY0zN/Xm6yTTTTrBU=; b=L+JBz2cHSc4c2mXvIAOyKIE2rwkyaxhTVOZjMZ/ks4t3iKw+X8F/ZcbF GRwFnV6wA3trJ68Sf/x4KupXo4GFOhr7Anek0js02goOR4vK08rVtAvMi ScemRJImHGkg+bpGCH3WCM7JOBamZ2NDtbWcfspujePoWY+fb3a6UTNcd k=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:47 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:45 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:28 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 0968D3AA3; Mon, 11 Apr 2022 15:20:27 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Date: Mon, 11 Apr 2022 15:20:15 +0530 Message-Id: <1649670615-21268-8-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx= 65.dtsi index 210e55c..8fef644 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -113,6 +113,12 @@ }; }; =20 + smem { + compatible =3D "qcom,smem"; + memory-region =3D <&smem_mem>; + hwlocks =3D <&tcsr_mutex 3>; + }; + soc: soc { #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.7.4