From nobody Thu May 14 06:36:10 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46C96C433F5 for ; Thu, 7 Apr 2022 15:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345115AbiDGPum (ORCPT ); Thu, 7 Apr 2022 11:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244584AbiDGPug (ORCPT ); Thu, 7 Apr 2022 11:50:36 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DA0F13F0A; Thu, 7 Apr 2022 08:48:33 -0700 (PDT) Date: Thu, 07 Apr 2022 15:48:30 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1649346512; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D10np9Fxcw/H9qvhVddoVVRVomltLLNcXei5XDaouJI=; b=jWg8H5/qHVCs68zQqE72YDyLnk7812K0jG84nIkyi2jubZiq3emmnjYGRWmQJOg0BQPxKB jH8lUKu+Cwc0djhzLNoT8jkdF4cvg7il/7SB9dkPGXVt7oi0WDZ3MXYPjns7Ww2I7F/hvF fMtqlfzGet8VHJ5SU/1zuJO17CZ3m6SRAGHTI8C98kig6T50930TZZ8y52wIFEj3eSDT6E mvU5li+j9hgIKHY9aiUpKxyRojGX6HOhQnhID2BKxVcxyZIgF8ZG5V18jxmM+Xbju7SKSX UWI0vik9Ptb5YrD2vZpodOhWRLqvNHhMh7fK7NuqDHzHYOY7E25+wDFUCPShDQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1649346512; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=D10np9Fxcw/H9qvhVddoVVRVomltLLNcXei5XDaouJI=; b=B3OQD4joMSdN9SCL5/XBeQGj0NQ2Ro+joZDHn9shdsiOSeXbZDZ9Uu0AP2RvCDibHldrIa zmAIW5YpzHoGOVBw== From: "tip-bot2 for Mike Travis" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/platform] x86/platform/uv: Update TSC sync state for UV5 Cc: Mike Travis , Steve Wahl , Borislav Petkov , Dimitri Sivanich , Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220406195149.228164-3-steve.wahl@hpe.com> References: <20220406195149.228164-3-steve.wahl@hpe.com> MIME-Version: 1.0 Message-ID: <164934651091.389.14325435214778502729.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/platform branch of tip: Commit-ID: bb3ab81bdbd53f88f26ffabc9fb15bd8466486ec Gitweb: https://git.kernel.org/tip/bb3ab81bdbd53f88f26ffabc9fb15bd84= 66486ec Author: Mike Travis AuthorDate: Wed, 06 Apr 2022 14:51:48 -05:00 Committer: Borislav Petkov CommitterDate: Thu, 07 Apr 2022 17:24:39 +02:00 x86/platform/uv: Update TSC sync state for UV5 The UV5 platform synchronizes the TSCs among all chassis, and will not proceed to OS boot without achieving synchronization. Previous UV platforms provided a register indicating successful synchronization. This is no longer available on UV5. On this platform TSC_ADJUST should not be reset by the kernel. Signed-off-by: Mike Travis Signed-off-by: Steve Wahl Signed-off-by: Borislav Petkov Reviewed-by: Dimitri Sivanich Acked-by: Thomas Gleixner Link: https://lore.kernel.org/r/20220406195149.228164-3-steve.wahl@hpe.com --- arch/x86/kernel/apic/x2apic_uv_x.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2ap= ic_uv_x.c index f5a48e6..a6e9c27 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,7 +199,13 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; =20 - /* Different returns from different UV BIOS versions */ + /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ + if (!is_uv(UV2|UV3|UV4)) { + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr =3D uv_early_read_mmr(UVH_TSC_SYNC_MMR); mmr_shift =3D is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;