From nobody Fri Jun 19 09:50:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6EC4C433EF for ; Tue, 5 Apr 2022 21:50:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1384983AbiDEVsu (ORCPT ); Tue, 5 Apr 2022 17:48:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1355853AbiDELz0 (ORCPT ); Tue, 5 Apr 2022 07:55:26 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 914A7BF4C; Tue, 5 Apr 2022 04:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649157203; x=1680693203; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=2ycaIj5IxG/RksZqMGqbZm+02qMbVViUT0wyO9DwMe4=; b=YMZc2pKgWT58kbxPwEqV3CURgBKT0HvzluLxsNsSX83mKNyefP6UaVfA j1Wru3wCiTcNSpv5jB3lW2al55GPWLbildF79CodME88fZSKTpQF6q+AV T9x0fX8nVad16FdDBm+e0zcy9SYwQeuK7xSpaP5kklzJqc5yRLMWqVS1I E=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 Apr 2022 04:13:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 04:13:09 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 04:13:09 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 04:13:04 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v6 1/2] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset Date: Tue, 5 Apr 2022 16:42:46 +0530 Message-ID: <1649157167-29106-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649157167-29106-1-git-send-email-quic_srivasam@quicinc.com> References: <1649157167-29106-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add AMP enable node and pinmux for primary and secondary I2S for SC7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 34 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 20 +++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 41 ++++++++++++++++++++++= ++++ 3 files changed, 95 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index dc17f20..de646d9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -530,6 +530,26 @@ ap_ec_spi: &spi10 { drive-strength =3D <2>; }; =20 +&pri_mi2s_data0 { + drive-strength =3D <6>; +}; + +&pri_mi2s_data1 { + drive-strength =3D <6>; +}; + +&pri_mi2s_mclk { + drive-strength =3D <6>; +}; + +&pri_mi2s_sclk { + drive-strength =3D <6>; +}; + +&pri_mi2s_ws { + drive-strength =3D <6>; +}; + &qspi_cs0 { bias-disable; drive-strength =3D <8>; @@ -610,6 +630,20 @@ ap_ec_spi: &spi10 { drive-strength =3D <10>; }; =20 +&sec_mi2s_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_ws { + drive-strength =3D <6>; +}; + /* PINCTRL - board-specific pinctrl */ =20 &pm7325_gpios { diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index ecbf2b8..2afbbe3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -462,7 +462,27 @@ drive-strength =3D <10>; }; =20 +&sec_mi2s_data0 { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_sclk { + drive-strength =3D <6>; + bias-disable; +}; + +&sec_mi2s_ws { + drive-strength =3D <6>; +}; + &tlmm { + amp_en: amp-en { + pins =3D "gpio63"; + bias-pull-down; + drive-strength =3D <2>; + }; + bt_en: bt-en { pins =3D "gpio85"; function =3D "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index f0b64be..8d8cec5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3527,6 +3527,31 @@ function =3D "pcie1_clkreqn"; }; =20 + pri_mi2s_data0: pri-mi2s-data0 { + pins =3D "gpio98"; + function =3D "mi2s0_data0"; + }; + + pri_mi2s_data1: pri-mi2s-data1 { + pins =3D "gpio99"; + function =3D "mi2s0_data1"; + }; + + pri_mi2s_mclk: pri-mi2s-mclk { + pins =3D "gpio96"; + function =3D "pri_mi2s"; + }; + + pri_mi2s_sclk: pri-mi2s-sclk { + pins =3D "gpio97"; + function =3D "mi2s0_sck"; + }; + + pri_mi2s_ws: pri-mi2s-ws { + pins =3D "gpio100"; + function =3D "mi2s0_ws"; + }; + qspi_clk: qspi-clk { pins =3D "gpio14"; function =3D "qspi_clk"; @@ -4261,6 +4286,22 @@ drive-strength =3D <2>; bias-bus-hold; }; + + sec_mi2s_data0: sec-mi2s-data0 { + pins =3D "gpio107"; + function =3D "mi2s1_data0"; + }; + + sec_mi2s_sclk: sec-mi2s-sclk { + pins =3D "gpio106"; + function =3D "mi2s1_sck"; + }; + + sec_mi2s_ws: sec-mi2s-ws { + pins =3D "gpio108"; + function =3D "mi2s1_ws"; + }; + }; =20 imem@146a5000 { --=20 2.7.4 From nobody Fri Jun 19 09:50:22 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B02BC4167B for ; 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Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 05 Apr 2022 04:13:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2022 04:13:13 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 04:13:13 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 04:13:09 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v6 2/2] arm64: dts: qcom: sc7280: add lpass lpi pin controller node Date: Tue, 5 Apr 2022 16:42:47 +0530 Message-ID: <1649157167-29106-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649157167-29106-1-git-send-email-quic_srivasam@quicinc.com> References: <1649157167-29106-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add LPASS LPI pinctrl node required for Audio functionality on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 98 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 +++++++++++++++++++++++++++= ++++ 2 files changed, 205 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 2afbbe3..f912a89 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -238,6 +238,104 @@ modem-init; }; =20 +&lpass_tlmm { + dmic01_active: dmic01-active { + clk { + drive-strength =3D <8>; + }; + + data { + drive-strength =3D <8>; + }; + }; + + dmic01_sleep: dmic01-sleep { + clk { + drive-strength =3D <2>; + bias-disable; + }; + + data { + drive-strength =3D <2>; + pull-down; + }; + }; + + dmic23_active: dmic02-active { + clk { + drive-strength =3D <8>; + }; + + data { + drive-strength =3D <8>; + }; + }; + + dmic23_sleep: dmic02-sleep { + clk { + drive-strength =3D <2>; + bias-disable; + }; + + data { + drive-strength =3D <2>; + pull-down; + }; + }; + + rx_swr_active: rx-swr-active { + clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + rx_swr_sleep: rx-swr-sleep { + clk { + drive-strength =3D <2>; + bias-pull-down; + }; + + data { + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + tx_swr_active: tx-swr-active { + clk { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + data { + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; + }; + + tx_swr_sleep: tx-swr-sleep { + clk { + drive-strength =3D <2>; + bias-pull-down; + }; + + data { + drive-strength =3D <2>; + bias-bus-hold; + }; + }; +}; + &pcie1 { status =3D "okay"; perst-gpio =3D <&tlmm 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 8d8cec5..db74fc3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1987,6 +1987,113 @@ qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + lpass_tlmm: pinctrl@33c0000 { + compatible =3D "qcom,sc7280-lpass-lpi-pinctrl"; + reg =3D <0 0x33c0000 0x0 0x20000>, + <0 0x3550000 0x0 0x10000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpass_tlmm 0 0 15>; + + #clock-cells =3D <1>; + + dmic01_active: dmic01-active { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + }; + + dmic01_sleep: dmic01-sleep { + clk { + pins =3D "gpio6"; + function =3D "dmic1_clk"; + }; + + data { + pins =3D "gpio7"; + function =3D "dmic1_data"; + }; + }; + + dmic23_active: dmic02-active { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + }; + + dmic23_sleep: dmic02-sleep { + clk { + pins =3D "gpio8"; + function =3D "dmic2_clk"; + }; + + data { + pins =3D "gpio9"; + function =3D "dmic2_data"; + }; + }; + + rx_swr_active: rx-swr-active { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + }; + + rx_swr_sleep: rx-swr-sleep { + clk { + pins =3D "gpio3"; + function =3D "swr_rx_clk"; + }; + + data { + pins =3D "gpio4", "gpio5"; + function =3D "swr_rx_data"; + }; + }; + + tx_swr_active: tx-swr-active { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + }; + + tx_swr_sleep: tx-swr-sleep { + clk { + pins =3D "gpio0"; + function =3D "swr_tx_clk"; + }; + + data { + pins =3D "gpio1", "gpio2", "gpio14"; + function =3D "swr_tx_data"; + }; + }; + }; + gpu: gpu@3d00000 { compatible =3D "qcom,adreno-635.0", "qcom,adreno"; reg =3D <0 0x03d00000 0 0x40000>, --=20 2.7.4