From nobody Fri Jun 19 11:03:05 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D962C433EF for ; Mon, 4 Apr 2022 21:49:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234639AbiDDVqR (ORCPT ); Mon, 4 Apr 2022 17:46:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380527AbiDDUVM (ORCPT ); Mon, 4 Apr 2022 16:21:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D40117E35; Mon, 4 Apr 2022 13:19:15 -0700 (PDT) Date: Mon, 04 Apr 2022 20:19:13 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1649103554; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=85Z+l0B/Lj9CU4s/mFSaflkVGrA6AqdwHS9uRiRp8VI=; b=JejzUKuEAcasSDsxDENPvC40qk6tXtnHSy0YPGnGu0zz7TIyedDnpyrTBruN+R40EiL1jD 0RYmlAS/HKMYDddhN3+iSo1Cj/ARUiJoqpOeLL31So66QHu7if//f5YSWG+45Fyz/hNotH +Lfvo0n0B3gevZjpo5i1WH+ZnNqoTksDKOujk7U9WY6oPFfoEbOefUQeUa0TVxHoLUrILb CzjtI6OrDDtAyYe1p7WrW3U2zIm89Ij6UTCn00FA0HkKUYW4b3R1e2IVIWYJYD6UoNMPnY Zw8XUdylutEwfzhXKpp5MEtXvTXTxtZt8+U+3x7d3E1qZbNo6XSN2TJe+Pg4pQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1649103554; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=85Z+l0B/Lj9CU4s/mFSaflkVGrA6AqdwHS9uRiRp8VI=; b=Dhymt3PXCGvOyJoQ9WDctUoe/ooMTOsPfeH87NULWzSJUu4WrJZbeh1qNniruIAkSWxTXY 1RKetKyQn6+WroAA== From: "tip-bot2 for Mike Travis" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/platform] x86/platform/uv: Update NMI Handler for UV5 Cc: Mike Travis , Borislav Petkov , Dimitri Sivanich , Steve Wahl , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220318224304.174967-2-mike.travis@hpe.com> References: <20220318224304.174967-2-mike.travis@hpe.com> MIME-Version: 1.0 Message-ID: <164910355342.389.4879516551285813736.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/platform branch of tip: Commit-ID: 419074a49f3343004a8bf5122e2a9a7259d7e4dd Gitweb: https://git.kernel.org/tip/419074a49f3343004a8bf5122e2a9a725= 9d7e4dd Author: Mike Travis AuthorDate: Fri, 18 Mar 2022 17:43:02 -05:00 Committer: Borislav Petkov CommitterDate: Mon, 04 Apr 2022 20:21:41 +02:00 x86/platform/uv: Update NMI Handler for UV5 Update NMI handler to interface with UV5 hardware. This involves changing the EVENT_OCCURRED MMR used by the hardware and removes the check for which NMI function is supported by UV BIOS. The newer NMI function is assumed supported on UV5 and above. Signed-off-by: Mike Travis Signed-off-by: Borislav Petkov Reviewed-by: Dimitri Sivanich Reviewed-by: Steve Wahl Link: https://lore.kernel.org/r/20220318224304.174967-2-mike.travis@hpe.com --- arch/x86/platform/uv/uv_nmi.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/x86/platform/uv/uv_nmi.c b/arch/x86/platform/uv/uv_nmi.c index 1e9ff28..6d2e9ae 100644 --- a/arch/x86/platform/uv/uv_nmi.c +++ b/arch/x86/platform/uv/uv_nmi.c @@ -244,8 +244,10 @@ static inline bool uv_nmi_action_is(const char *action) /* Setup which NMI support is present in system */ static void uv_nmi_setup_mmrs(void) { + bool nmi_supported =3D false; + /* First determine arch specific MMRs to handshake with BIOS */ - if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) { + if (UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK) { /* UV2,3,4 setup */ uvh_nmi_mmrx =3D UVH_EVENT_OCCURRED0; uvh_nmi_mmrx_clear =3D UVH_EVENT_OCCURRED0_ALIAS; uvh_nmi_mmrx_shift =3D UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT; @@ -255,26 +257,25 @@ static void uv_nmi_setup_mmrs(void) uvh_nmi_mmrx_req =3D UVH_BIOS_KERNEL_MMR_ALIAS_2; uvh_nmi_mmrx_req_shift =3D 62; =20 - } else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) { + } else if (UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK) { /* UV5+ setup */ uvh_nmi_mmrx =3D UVH_EVENT_OCCURRED1; uvh_nmi_mmrx_clear =3D UVH_EVENT_OCCURRED1_ALIAS; uvh_nmi_mmrx_shift =3D UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT; uvh_nmi_mmrx_type =3D "OCRD1-EXTIO_INT0"; =20 - uvh_nmi_mmrx_supported =3D UVH_EXTIO_INT0_BROADCAST; - uvh_nmi_mmrx_req =3D UVH_BIOS_KERNEL_MMR_ALIAS_2; - uvh_nmi_mmrx_req_shift =3D 62; + nmi_supported =3D true; /* assume sync valid on UV5+ */ + uvh_nmi_mmrx_req =3D 0; /* no request bit to clear */ =20 } else { - pr_err("UV:%s:cannot find EVENT_OCCURRED*_EXTIO_INT0\n", - __func__); + pr_err("UV:%s:NMI support not available on this system\n", __func__); return; } =20 /* Then find out if new NMI is supported */ - if (likely(uv_read_local_mmr(uvh_nmi_mmrx_supported))) { - uv_write_local_mmr(uvh_nmi_mmrx_req, - 1UL << uvh_nmi_mmrx_req_shift); + if (likely(nmi_supported) || (uv_read_local_mmr(uvh_nmi_mmrx_supported)))= { + if (uvh_nmi_mmrx_req) + uv_write_local_mmr(uvh_nmi_mmrx_req, + 1UL << uvh_nmi_mmrx_req_shift); nmi_mmr =3D uvh_nmi_mmrx; nmi_mmr_clear =3D uvh_nmi_mmrx_clear; nmi_mmr_pending =3D 1UL << uvh_nmi_mmrx_shift;