From nobody Fri Jun 19 11:03:06 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F064C4167E for ; Mon, 4 Apr 2022 21:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378954AbiDDV6P (ORCPT ); Mon, 4 Apr 2022 17:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1380526AbiDDUVM (ORCPT ); Mon, 4 Apr 2022 16:21:12 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09CC317E19; Mon, 4 Apr 2022 13:19:14 -0700 (PDT) Date: Mon, 04 Apr 2022 20:19:12 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1649103553; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QZQaYr09f3K/gGOi6unzAYjbezIKt+jwMzKppsteJ8g=; b=di7iGq60peohiF1pGjIv56WNkKgziqE8Wge457uTEcrV+4r33kTjcbKK416KzLj6jKutKi akPJGxr+Xjop0R6Ij/OV2cwyVVv7jpxg52rO784tx0OnWSOXcrseXW4L4qx7SFEjx5bqVw QqD+LaTP0bXiRh3fF3Vrw9TjK3LTbMQhjeDCtlNgOj8tKuHjiVfwHXqFnSs8rr3pGxBBqN e+KIb7C09JzZ/4/B7H0qJUlgbynHM1fo4duneeqk0I5v/1IuR3EaCmVY0+qtVPUBics1Fl DgOQaiNzXa7xsQGDVE6HnbCLBVL7Czlx9HDLsV4kBMX88gN70ndSkXpl4KUblw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1649103553; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QZQaYr09f3K/gGOi6unzAYjbezIKt+jwMzKppsteJ8g=; b=SgycpArjwOUpnjfW/PUk1RLKscUzwcYD9WsWHR12s51VvMpG8xytI1Knbvggq8u+z8fMBO awZzRGTNCWR1PLBg== From: "tip-bot2 for Mike Travis" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: x86/platform] x86/platform/uv: Update TSC sync state for UV5 Cc: Mike Travis , Borislav Petkov , Dimitri Sivanich , Steve Wahl , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220318224304.174967-3-mike.travis@hpe.com> References: <20220318224304.174967-3-mike.travis@hpe.com> MIME-Version: 1.0 Message-ID: <164910355241.389.1602942943819019467.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the x86/platform branch of tip: Commit-ID: 4395de040d24b40fb3cd7fb4f0b013748abe0a72 Gitweb: https://git.kernel.org/tip/4395de040d24b40fb3cd7fb4f0b013748= abe0a72 Author: Mike Travis AuthorDate: Fri, 18 Mar 2022 17:43:03 -05:00 Committer: Borislav Petkov CommitterDate: Mon, 04 Apr 2022 20:21:44 +02:00 x86/platform/uv: Update TSC sync state for UV5 Update TSC to not check TSC sync state for uv5+ as it is not available. It is assumed that TSC will always be in sync for multiple chassis and will pass the tests for the kernel to accept it as the clocksource. To disable this check use the kernel start options tsc=3Dreliable clocksource=3Dtsc. Signed-off-by: Mike Travis Signed-off-by: Borislav Petkov Reviewed-by: Dimitri Sivanich Reviewed-by: Steve Wahl Link: https://lore.kernel.org/r/20220318224304.174967-3-mike.travis@hpe.com --- arch/x86/kernel/apic/x2apic_uv_x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2ap= ic_uv_x.c index f5a48e6..387d653 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c @@ -199,10 +199,16 @@ static void __init uv_tsc_check_sync(void) int mmr_shift; char *state; =20 - /* Different returns from different UV BIOS versions */ + /* UV5+, sync state from bios not available, assumed valid */ + if (!is_uv(UV2|UV3|UV4)) { + pr_debug("UV: TSC sync state for UV5+ assumed valid\n"); + mark_tsc_async_resets("UV5+"); + return; + } + + /* UV2,3,4, UV BIOS TSC sync state available */ mmr =3D uv_early_read_mmr(UVH_TSC_SYNC_MMR); - mmr_shift =3D - is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; + mmr_shift =3D is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; sync_state =3D (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; =20 /* Check if TSC is valid for all sockets */