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Sun, 27 Mar 2022 23:15:33 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , , , , Sameer Pujar Subject: [RFC PATCH v2 1/6] ASoC: dt-bindings: Convert rt5659 bindings to YAML schema Date: Mon, 28 Mar 2022 11:44:05 +0530 Message-ID: <1648448050-15237-2-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1648448050-15237-1-git-send-email-spujar@nvidia.com> References: <1648448050-15237-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff7cb7e4-eb39-44b0-3eb6-08da10826170 X-MS-TrafficTypeDiagnostic: DM6PR12MB4339:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Tukb/HflDEajp2Cj1eH0lDmBexfeajsMH2sZXUSDfQ0YnS4F/2PMEjeCRedDv2yMgCRKnnZAIv83iMSXiF0AA56k9sypijkY+xUXbp7rZNTSv0mmknSrMCqBvE7r/6rXag/fxP3Q8FP0nijKfKRAx+1Fgfjq4QTRzejLqyhYOTb3ZVxjLQ+062e9li+GKf15+oiM5Ns/lZsDWRm3OwMs/dL3ImdJsmfxT6hDL8JqRLIKMorOr+oTxhtrz9ZBBmH4DnxEZLow1qPsY2jimcMLNzU2kbikjBiflGAU3vNI9VFrVPwGYsN5/e1O5qFBkSqhXQKzu816X00RaBinCZtO1z0D3G5oLVCnKs3p1lcb589JoLBoG4HoVTC2PAv6ltx8Ew6Sdoo2mfNZfX/jrbe6H/TeQ3dhXeMwVMKk53f0e4vQd3IXQDF9RITtDaJX6jZQgHtXIhfG5p4lvjN2mYcp94mcGpXlXd5iY4F/GQSGzQBWT784eRRSiIDkrXlAcO87VMRJ86Spth2Mee61u6TPceA5BdENjvgwLM0iaerDFTQRRObT2Pz7+MTV2SzNYl/dMbDNxABGjX4jYnn1M59gMF5nzIF5Ts7gSzBof4pyb1UXB6JfE4Xnz3alqISX+N26Ox7qQnDffw8nudVzYxJw+IRmvlUWIjYyz/YKNDCOuxm1Fh/J/u7rtljYlIBzOi/JcMUPUKf4tR0PPZ/RlHhG+JtqYung8AOm1koIK5OAEpx8rg/OukJSF6SVG9uTk0tlSh963jzfvzkMupsp7NKokwOI5D+35CNpcrcbATK4LtHCsC8mIVPk51oE9jPWqDLnnNRfA2JT4pVUraND//bBdA== X-Forefront-Antispam-Report: CIP:12.22.5.235;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(356005)(40460700003)(186003)(110136005)(54906003)(81166007)(316002)(8676002)(508600001)(966005)(47076005)(36756003)(86362001)(5660300002)(2906002)(4326008)(70206006)(70586007)(2616005)(8936002)(7416002)(426003)(82310400004)(336012)(7696005)(36860700001)(83380400001)(26005)(107886003)(6666004)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:15:39.1791 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff7cb7e4-eb39-44b0-3eb6-08da10826170 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4339 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Convert rt5659.txt DT binding to YAML schema. This binding is applicable to rt5658 and rt5659 audio CODECs. Signed-off-by: Sameer Pujar Cc: Oder Chiou --- .../devicetree/bindings/sound/realtek,rt5659.yaml | 112 +++++++++++++++++= ++++ Documentation/devicetree/bindings/sound/rt5659.txt | 89 ---------------- 2 files changed, 112 insertions(+), 89 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/realtek,rt5659.= yaml delete mode 100644 Documentation/devicetree/bindings/sound/rt5659.txt diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/= Documentation/devicetree/bindings/sound/realtek,rt5659.yaml new file mode 100644 index 0000000..3bd9b6f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,rt5659.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RT5658 and RT5659 audio CODECs + +description: This device supports I2C only. + +maintainers: + - Oder Chiou + +allOf: + - $ref: name-prefix.yaml# + +properties: + compatible: + enum: + - realtek,rt5658 + - realtek,rt5659 + + reg: + description: The I2C address of the device + maxItems: 1 + + interrupts: + description: The CODEC's interrupt output + maxItems: 1 + + clocks: + items: + - description: Master clock (MCLK) to the CODEC + + clock-names: + items: + - const: mclk + + realtek,in1-differential: + description: MIC1 input is differntial and not single-ended. + type: boolean + + realtek,in3-differential: + description: MIC3 input is differntial and not single-ended. + type: boolean + + realtek,in4-differential: + description: MIC3 input is differntial and not single-ended. + type: boolean + + realtek,dmic1-data-pin: + description: DMIC1 data pin usage + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # dmic1 is not used + - 1 # using IN2N pin as dmic1 data pin + - 2 # using GPIO5 pin as dmic1 data pin + - 3 # using GPIO9 pin as dmic1 data pin + - 4 # using GPIO11 pin as dmic1 data pin + + realtek,dmic2-data-pin: + description: DMIC2 data pin usage + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # dmic2 is not used + - 1 # using IN2P pin as dmic2 data pin + - 2 # using GPIO6 pin as dmic2 data pin + - 3 # using GPIO10 pin as dmic2 data pin + - 4 # using GPIO12 pin as dmic2 data pin + + realtek,jd-src: + description: Jack detect source + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # No JD is used + - 1 # using JD3 as JD source + - 2 # JD source for Intel HDA header + + realtek,ldo1-en-gpios: + description: The GPIO that controls the CODEC's LDO1_EN pin. + + realtek,reset-gpios: + description: The GPIO that controls the CODEC's RESET pin. + + sound-name-prefix: true + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + audio-codec@1a { + compatible =3D "realtek,rt5658"; + reg =3D <0x1a>; + interrupt-parent =3D <&gpio>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA194_CLK_AUD_MCLK>; + clock-names =3D "mclk"; + realtek,jd-src =3D <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/rt5659.txt b/Documenta= tion/devicetree/bindings/sound/rt5659.txt deleted file mode 100644 index 013f534..0000000 --- a/Documentation/devicetree/bindings/sound/rt5659.txt +++ /dev/null @@ -1,89 +0,0 @@ -RT5659/RT5658 audio CODEC - -This device supports I2C only. - -Required properties: - -- compatible : One of "realtek,rt5659" or "realtek,rt5658". - -- reg : The I2C address of the device. - -- interrupts : The CODEC's interrupt output. - -Optional properties: - -- clocks: The phandle of the master clock to the CODEC -- clock-names: Should be "mclk" - -- realtek,in1-differential -- realtek,in3-differential -- realtek,in4-differential - Boolean. Indicate MIC1/3/4 input are differential, rather than single-en= ded. - -- realtek,dmic1-data-pin - 0: dmic1 is not used - 1: using IN2N pin as dmic1 data pin - 2: using GPIO5 pin as dmic1 data pin - 3: using GPIO9 pin as dmic1 data pin - 4: using GPIO11 pin as dmic1 data pin - -- realtek,dmic2-data-pin - 0: dmic2 is not used - 1: using IN2P pin as dmic2 data pin - 2: using GPIO6 pin as dmic2 data pin - 3: using GPIO10 pin as dmic2 data pin - 4: using GPIO12 pin as dmic2 data pin - -- realtek,jd-src - 0: No JD is used - 1: using JD3 as JD source - 2: JD source for Intel HDA header - -- realtek,ldo1-en-gpios : The GPIO that controls the CODEC's LDO1_EN pin. -- realtek,reset-gpios : The GPIO that controls the CODEC's RESET pin. - -- sound-name-prefix: Please refer to name-prefix.yaml - -- ports: A Codec may have a single or multiple I2S interfaces. These - interfaces on Codec side can be described under 'ports' or 'port'. - When the SoC or host device is connected to multiple interfaces of - the Codec, the connectivity can be described using 'ports' property. - If a single interface is used, then 'port' can be used. The usage - depends on the platform or board design. - Please refer to Documentation/devicetree/bindings/graph.txt - -Pins on the device (for linking into audio routes) for RT5659/RT5658: - - * DMIC L1 - * DMIC R1 - * DMIC L2 - * DMIC R2 - * IN1P - * IN1N - * IN2P - * IN2N - * IN3P - * IN3N - * IN4P - * IN4N - * HPOL - * HPOR - * SPOL - * SPOR - * LOUTL - * LOUTR - * MONOOUT - * PDML - * PDMR - * SPDIF - -Example: - -rt5659 { - compatible =3D "realtek,rt5659"; - reg =3D <0x1b>; - interrupt-parent =3D <&gpio>; - interrupts =3D ; - realtek,ldo1-en-gpios =3D - <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>; -}; --=20 2.7.4 From nobody Tue Jun 23 05:05:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52970C433EF for ; Mon, 28 Mar 2022 06:15:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238366AbiC1GRe (ORCPT ); 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Mon, 28 Mar 2022 06:15:43 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 27 Mar 2022 23:15:42 -0700 Received: from audio.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Sun, 27 Mar 2022 23:15:38 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , , , , Sameer Pujar Subject: [RFC PATCH v2 2/6] ASoC: dt-bindings: Add audio-graph-port bindings to rt5659 Date: Mon, 28 Mar 2022 11:44:06 +0530 Message-ID: <1648448050-15237-3-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1648448050-15237-1-git-send-email-spujar@nvidia.com> References: <1648448050-15237-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 57391aba-7eae-40cf-0626-08da10826464 X-MS-TrafficTypeDiagnostic: DM4PR12MB6010:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:15:44.1322 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 57391aba-7eae-40cf-0626-08da10826464 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6010 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To use rt5658 or rt5659 audio CODEC with generic audio-graph-card machine driver, the CODEC requires "port" bindings. Thus add "audio-graph-port" reference to the rt5659 binding. Signed-off-by: Sameer Pujar Cc: Oder Chiou --- Documentation/devicetree/bindings/sound/realtek,rt5659.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/= Documentation/devicetree/bindings/sound/realtek,rt5659.yaml index 3bd9b6f..b0485b8 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml @@ -84,6 +84,10 @@ properties: =20 sound-name-prefix: true =20 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + additionalProperties: false =20 required: --=20 2.7.4 From nobody Tue Jun 23 05:05:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C316C4332F for ; Mon, 28 Mar 2022 06:16:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238370AbiC1GRm (ORCPT ); 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Mon, 28 Mar 2022 06:15:48 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 27 Mar 2022 23:15:47 -0700 Received: from audio.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Sun, 27 Mar 2022 23:15:43 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , , , , Sameer Pujar Subject: [RFC PATCH v2 3/6] ASoC: dt-bindings: Extend clock bindings of rt5659 Date: Mon, 28 Mar 2022 11:44:07 +0530 Message-ID: <1648448050-15237-4-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1648448050-15237-1-git-send-email-spujar@nvidia.com> References: <1648448050-15237-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ff197eb2-2888-41e8-7849-08da108266f5 X-MS-TrafficTypeDiagnostic: BY5PR12MB3697:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:15:48.4252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff197eb2-2888-41e8-7849-08da108266f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3697 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The rt5658 or rt5659 CODEC system clock (SYSCLK) can be derived from various clock sources. For example it can be derived either from master clock (MCLK) or by internal PLL. The internal PLL again can take input clock references from bit clocks (BCLKs) and MCLK. To enable a flexible clocking configuration the DT binding is extended here. It makes use of standard clock bindings and sets up the clock relation via DT. Signed-off-by: Sameer Pujar Cc: Oder Chiou --- .../devicetree/bindings/sound/realtek,rt5659.yaml | 53 ++++++++++++++++++= ++-- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml b/= Documentation/devicetree/bindings/sound/realtek,rt5659.yaml index b0485b8..0c2f3cb 100644 --- a/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml +++ b/Documentation/devicetree/bindings/sound/realtek,rt5659.yaml @@ -29,12 +29,28 @@ properties: maxItems: 1 =20 clocks: - items: - - description: Master clock (MCLK) to the CODEC + description: | + CODEC can receive multiple clock inputs like Master + clock (MCLK), I2S bit clocks (BCLK1, BCLK2, BCLK3, + BCLK4). The CODEC SYSCLK can be generated from MCLK + or internal PLL. In turn PLL can reference from MCLK + and BCLKs. =20 clock-names: - items: - - const: mclk + description: | + The clock names can be combination of following: + "mclk" : Master clock + "pll_ref" : Reference to CODEC PLL clock + "sysclk" : CODEC SYSCLK + "^bclk[1-4]$" : Bit clocks to CODEC + + "#clock-cells": + const: 1 + + clock-output-names: + description: PLL output clock + $ref: /schemas/types.yaml#/definitions/string + const: rt5659_pll_out =20 realtek,in1-differential: description: MIC1 input is differntial and not single-ended. @@ -97,6 +113,7 @@ required: =20 examples: - | + /* SYSCLK derived from MCLK */ #include #include =20 @@ -114,3 +131,31 @@ examples: realtek,jd-src =3D <2>; }; }; + + - | + /* + * SYSCLK is derived from CODEC internal PLL and PLL uses I2S1 BCLK + * as the clock reference. + */ + #include + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + rt5658: audio-codec@1a { + compatible =3D "realtek,rt5658"; + reg =3D <0x1a>; + interrupt-parent =3D <&gpio>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA194_CLK_AUD_MCLK>, + <&bpmp TEGRA194_CLK_I2S1>, + <&bpmp TEGRA194_CLK_I2S1>, + <&rt5658 0>; + clock-names =3D "mclk", "bclk1", "pll_ref", "sysclk"; + #clock-cells =3D <1>; + clock-output-names =3D "rt5659_pll_out"; + realtek,jd-src =3D <2>; + }; + }; --=20 2.7.4 From nobody Tue Jun 23 05:05:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1727C433EF for ; Mon, 28 Mar 2022 06:16:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238362AbiC1GRp (ORCPT ); Mon, 28 Mar 2022 02:17:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34088 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238391AbiC1GRk (ORCPT ); Mon, 28 Mar 2022 02:17:40 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam08on2063.outbound.protection.outlook.com [40.107.102.63]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A89182B276; 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Mon, 28 Mar 2022 06:15:52 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sun, 27 Mar 2022 23:15:52 -0700 Received: from audio.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Sun, 27 Mar 2022 23:15:47 -0700 From: Sameer Pujar To: , , , , , , , CC: , , , , , , , Sameer Pujar Subject: [RFC PATCH v2 4/6] ASoC: soc-pcm: tweak DPCM BE hw_param() call order Date: Mon, 28 Mar 2022 11:44:08 +0530 Message-ID: <1648448050-15237-5-git-send-email-spujar@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1648448050-15237-1-git-send-email-spujar@nvidia.com> References: <1648448050-15237-1-git-send-email-spujar@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 25187317-a0ec-4c08-8cd0-08da10826abc X-MS-TrafficTypeDiagnostic: MW2PR12MB2379:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:15:54.7162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25187317-a0ec-4c08-8cd0-08da10826abc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW2PR12MB2379 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For DPCM links, the order of hw_param() call depends on the sequence of BE connection to FE. It is possible that one BE link can provide clock to another BE link. In such cases consumer BE DAI, to get the rate set by provider BE DAI, can use the standard clock functions only if provider has already set the appropriate rate during its hw_param() stage. Presently the order is fixed and does not depend on the provider and consumer relationships. So the clock rates need to be known ahead of hw_param() stage. This patch tweaks the hw_param() order by connecting the provider BEs late to a FE. With this hw_param() calls for provider BEs happen first and then followed by consumer BEs. The consumers can use the standard clk_get_rate() function to get the rate of the clock they depend on. Signed-off-by: Sameer Pujar --- TODO: * The FE link is not considered in this. For Tegra it is fine to call hw_params() for FE at the end. But systems, which want to apply this tweak for FE as well, have to extend this tweak to FE. * Also only DPCM is considered here. If normal links require such tweak, it needs to be extended. sound/soc/soc-pcm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 59 insertions(+), 1 deletion(-) diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c index 9a95468..5829514 100644 --- a/sound/soc/soc-pcm.c +++ b/sound/soc/soc-pcm.c @@ -1442,6 +1442,29 @@ static int dpcm_prune_paths(struct snd_soc_pcm_runti= me *fe, int stream, return prune; } =20 +static bool defer_dpcm_be_connect(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_dai *dai; + int i; + + if (!(rtd->dai_link->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK)) + return false; + + if ((rtd->dai_link->dai_fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) =3D=3D + SND_SOC_DAIFMT_CBC_CFC) { + + for_each_rtd_cpu_dais(rtd, i, dai) { + + if (!snd_soc_dai_is_dummy(dai)) + return true; + } + } + + return false; +} + +#define MAX_CLK_PROVIDER_BE 10 + static int dpcm_add_paths(struct snd_soc_pcm_runtime *fe, int stream, struct snd_soc_dapm_widget_list **list_) { @@ -1449,7 +1472,8 @@ static int dpcm_add_paths(struct snd_soc_pcm_runtime = *fe, int stream, struct snd_soc_dapm_widget_list *list =3D *list_; struct snd_soc_pcm_runtime *be; struct snd_soc_dapm_widget *widget; - int i, new =3D 0, err; + struct snd_soc_pcm_runtime *prov[MAX_CLK_PROVIDER_BE]; + int i, new =3D 0, err, count =3D 0; =20 /* Create any new FE <--> BE connections */ for_each_dapm_widgets(list, i, widget) { @@ -1489,6 +1513,40 @@ static int dpcm_add_paths(struct snd_soc_pcm_runtime= *fe, int stream, (be->dpcm[stream].state !=3D SND_SOC_DPCM_STATE_CLOSE)) continue; =20 + /* Connect clock provider BEs at the end */ + if (defer_dpcm_be_connect(be)) { + if (count >=3D MAX_CLK_PROVIDER_BE) { + dev_err(fe->dev, "ASoC: too many clock provider BEs\n"); + return -EINVAL; + } + + prov[count++] =3D be; + continue; + } + + /* newly connected FE and BE */ + err =3D dpcm_be_connect(fe, be, stream); + if (err < 0) { + dev_err(fe->dev, "ASoC: can't connect %s\n", + widget->name); + break; + } else if (err =3D=3D 0) /* already connected */ + continue; + + /* new */ + dpcm_set_be_update_state(be, stream, SND_SOC_DPCM_UPDATE_BE); + new++; + } + + /* + * Now connect clock provider BEs. A late connection means, + * these BE links appear first in the list maintained by FE + * and hw_param() call for these happen first. + */ + for (i =3D 0; i < count; i++) { + + be =3D prov[i]; + /* newly connected FE and BE */ err =3D dpcm_be_connect(fe, be, stream); if (err < 0) { --=20 2.7.4 From nobody Tue Jun 23 05:05:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6BFF6C433EF for ; Mon, 28 Mar 2022 06:16:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238398AbiC1GRv (ORCPT ); Mon, 28 Mar 2022 02:17:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238374AbiC1GRm (ORCPT ); Mon, 28 Mar 2022 02:17:42 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1anam02on2055.outbound.protection.outlook.com [40.107.96.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7557E27FF3; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:15:58.0064 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 130dcd6b-df31-4a8c-d22c-08da10826cad X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT040.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4181 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RT5658 or RT5659 codecs have multiple options to derive Sysclk: * Sysclk sourced from MCLK clock supplied by SoC * Sysclk sourced from codec internal PLL. The PLL again can take reference from I2S BCLKs and MCLK. * Sysclk sourced from RCCLK. The clock relationship for codec is as following: |\ | \ |\ BCLK1 ---->| \ RCCLK | \ | \ |----------->| \ BCLK2 ---->| M \ ____________ | \ | U | | | PLL output | M \ BCLK3 ---->| X |----->| Codec PLL |---------------->| U | | | |____________| | X |----> Sysclk BCLK4 ---->| / |----->| | | / | | / MCLK ---->| / | | / | |/ | | / | MCLK | |/ |_______________________________________| Presently 'snd_soc_component_driver' and 'snd_soc_dai_driver' expose callbacks, set_sysclk() for Sysclk and set_pll() for PLL configurations, which are implemented on codec driver side. The generic machine drivers (simple-card or audio-graph-card) depend on default values for Sysclk source or PLL reference. Specific clock relationships are not supported. The simpler solution would be to expose new DT binding properties to convey the PLL and Sysclk source. This attempt was made before with [0], but was not encouraged because it tries to do the same thing what standard clock bindings already provide This patch uses standard clock bindings to establish the codec clock relationships. Specific configurations can be applied by DT bindings from codec device node. The codec driver registers PLL and MUX clocks to provide this flexibility. [0] https://patchwork.kernel.org/project/alsa-devel/list/?series=3D438531&a= rchive=3Dboth&state=3D* Signed-off-by: Sameer Pujar Cc: Oder Chiou --- Note: If such model is OK, other codec drivers will require similar handling. Objective is to drive clock relationships from DT using standard clock bindings. With this machine driver need not know the details for configuring codec PLL or other clocks and thus can be more generic. sound/soc/codecs/rt5659.c | 248 ++++++++++++++++++++++++++++++++++++++++++= ++-- sound/soc/codecs/rt5659.h | 9 ++ 2 files changed, 249 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/rt5659.c b/sound/soc/codecs/rt5659.c index e1503c2..3bf9680 100644 --- a/sound/soc/codecs/rt5659.c +++ b/sound/soc/codecs/rt5659.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -18,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -3527,6 +3530,9 @@ static int rt5659_set_component_pll(struct snd_soc_co= mponent *component, int pll rt5659->pll_out =3D freq_out; rt5659->pll_src =3D source; =20 + dev_dbg(component->dev, "pll_in =3D %u Hz, pll_out =3D %u Hz, pll_src =3D= %d\n", + freq_in, freq_out, source); + return 0; } =20 @@ -3843,6 +3849,237 @@ static int rt5659_parse_dt(struct rt5659_priv *rt56= 59, struct device *dev) return 0; } =20 +static unsigned long rt5659_pll_recalc_rate(struct clk_hw *hw, unsigned lo= ng parent_rate) +{ + struct rt5659_priv *rt5659 =3D + container_of(hw, struct rt5659_priv, clk_pll_out); + + return rt5659->pll_out; +} + +static long rt5659_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static int rt5659_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct rt5659_priv *rt5659 =3D + container_of(hw, struct rt5659_priv, clk_pll_out); + + rt5659->pll_out =3D rate; + + return 0; +} + +static const struct clk_ops rt5659_pll_out_ops =3D { + .recalc_rate =3D &rt5659_pll_recalc_rate, + .round_rate =3D &rt5659_pll_round_rate, + .set_rate =3D &rt5659_pll_set_rate, +}; + +static int rt5659_setup_clk(struct snd_soc_dai *dai, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_component *component =3D dai->component; + struct rt5659_priv *rt5659 =3D snd_soc_component_get_drvdata(component); + int ret, sysclk_src; + + /* + * Update the clock rate if Codec is driving it. The consumers + * can use clk_get_rate() function to get the rate. + */ + if (rt5659->master[dai->id] && rt5659->clk_bclk[dai->id]) { + unsigned int bclk_rate =3D params_rate(params) * + params_width(params) * + params_channels(params); + + clk_set_rate(rt5659->clk_bclk[dai->id], bclk_rate); + } + + if (rt5659->clk_sysclk_src) { + sysclk_src =3D clk_hw_get_parent_index(rt5659->clk_sysclk_src); + + ret =3D rt5659_set_component_sysclk(component, sysclk_src, 0, + rt5659->sysclk, 0); + if (ret) + return ret; + } + + if (rt5659->clk_pll_src && (sysclk_src =3D=3D RT5659_SCLK_S_PLL1)) { + unsigned int pll_src =3D + clk_hw_get_parent_index(rt5659->clk_pll_src); + unsigned int freq_in =3D clk_get_rate(rt5659->clk_pll_src->clk); + + ret =3D rt5659_set_component_pll(component, 0, pll_src, + freq_in, rt5659->sysclk); + if (ret) + return ret; + } + + return 0; +} + +static int rt5659_register_clks(struct device *dev, struct rt5659_priv *rt= 5659) +{ + const struct clk_hw *sysclk_clk_hw[RT5659_NUM_SCLK_SRC_CLKS] =3D { NULL }; + const char *pnames_sysclk[RT5659_NUM_SCLK_SRC_CLKS] =3D { NULL }; + const char *pnames_pll[RT5659_NUM_PLL1_SRC_CLKS] =3D { NULL }; + struct clk_init_data init =3D { }; + static void __iomem *clk_base; + const char *clk_name; + int ret, i, count_pll_src =3D 0, count_sysclk_src =3D 0; + + /* Check if MCLK provided */ + rt5659->mclk =3D devm_clk_get(dev, "mclk"); + if (IS_ERR(rt5659->mclk)) { + if (PTR_ERR(rt5659->mclk) !=3D -ENOENT) + return PTR_ERR(rt5659->mclk); + /* Otherwise mark the mclk pointer to NULL */ + rt5659->mclk =3D NULL; + } + + if (!of_find_property(dev->of_node, "#clock-cells", NULL)) + return 0; + + /* Get PLL source */ + rt5659->pll_ref =3D devm_clk_get(dev, "pll_ref"); + if (IS_ERR(rt5659->pll_ref)) { + if (PTR_ERR(rt5659->pll_ref) !=3D -ENOENT) + return PTR_ERR(rt5659->pll_ref); + + rt5659->pll_ref =3D NULL; + } + + /* Possible parents for PLL */ + if (rt5659->mclk) { + pnames_pll[count_pll_src] =3D __clk_get_name(rt5659->mclk); + count_pll_src++; + } + + for (i =3D 0; i < RT5659_AIFS; i++) { + char name[50]; + + memset(name, '\0', sizeof(name)); + snprintf(name, sizeof(name), "%s%d", "bclk", i + 1); + + rt5659->clk_bclk[i] =3D devm_clk_get(dev, name); + if (IS_ERR(rt5659->clk_bclk[i])) { + if (PTR_ERR(rt5659->clk_bclk[i]) !=3D -ENOENT) + return PTR_ERR(rt5659->clk_bclk[i]); + + rt5659->clk_bclk[i] =3D NULL; + continue; + } + + pnames_pll[count_pll_src] =3D __clk_get_name(rt5659->clk_bclk[i]); + count_pll_src++; + } + + clk_base =3D devm_kzalloc(dev, sizeof(char) * 4, GFP_KERNEL); + + /* Register MUX for PLL source */ + rt5659->clk_pll_src =3D clk_hw_register_mux(dev, "rt5659_pll_ref", + pnames_pll, count_pll_src, + CLK_SET_RATE_PARENT, + clk_base, 0, 1, 0, NULL); + + ret =3D of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + rt5659->clk_pll_src); + if (ret) { + dev_err(dev, "failed to register clk hw\n"); + return ret; + } + + if (rt5659->pll_ref) { + ret =3D clk_set_parent(rt5659->clk_pll_src->clk, rt5659->pll_ref); + if (ret) { + dev_err(dev, "failaed to set parent for clk %s\n", + __clk_get_name(rt5659->clk_pll_src->clk)); + return ret; + } + } + + /* Register PLL out clock */ + if (of_property_read_string(dev->of_node, "clock-output-names", + (const char **) &clk_name)) + clk_name =3D "rt5659_pll_out"; + + init.name =3D clk_name; + init.ops =3D &rt5659_pll_out_ops; + init.flags =3D CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE; + init.parent_hws =3D (const struct clk_hw **) &rt5659->clk_pll_src; + init.num_parents =3D 1; + + rt5659->clk_pll_out.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &rt5659->clk_pll_out); + if (ret) { + dev_err(dev, "failed to register PLL clock HW\n"); + return ret; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + &rt5659->clk_pll_out); + if (ret) { + dev_err(dev, "failed to add PLL clock provider\n"); + return ret; + } + + /* Get sysclk source */ + rt5659->sysclk_ref =3D devm_clk_get(dev, "sysclk"); + if (IS_ERR(rt5659->sysclk_ref)) { + if (PTR_ERR(rt5659->sysclk_ref) !=3D -ENOENT) + return PTR_ERR(rt5659->sysclk_ref); + + rt5659->sysclk_ref =3D NULL; + } + + /* Possible parents for Sysclk */ + if (rt5659->mclk) { + /* For sysclk */ + pnames_sysclk[count_sysclk_src] =3D __clk_get_name(rt5659->mclk); + sysclk_clk_hw[count_sysclk_src] =3D __clk_get_hw(rt5659->mclk); + count_sysclk_src++; + } + + if (rt5659->clk_pll_out.clk) { + pnames_sysclk[count_sysclk_src] =3D __clk_get_name(rt5659->clk_pll_out.c= lk); + sysclk_clk_hw[count_sysclk_src] =3D __clk_get_hw(rt5659->clk_pll_out.clk= ); + count_sysclk_src++; + } + + /* Register MUX for sysclk source */ + rt5659->clk_sysclk_src =3D __clk_hw_register_mux(dev, dev->of_node, + "rt5659_sysclk", + count_sysclk_src, + pnames_sysclk, + sysclk_clk_hw, NULL, + CLK_SET_RATE_PARENT, + clk_base, 0, 1, 0, + NULL, NULL); + + ret =3D of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, + rt5659->clk_sysclk_src); + if (ret) { + dev_err(dev, "failed to register clk hw\n"); + return ret; + } + + if (rt5659->sysclk_ref) { + ret =3D clk_set_parent(rt5659->clk_sysclk_src->clk, rt5659->sysclk_ref); + if (ret) { + dev_err(dev, "failed to set parent for clk %s\n", + __clk_get_name(rt5659->clk_sysclk_src->clk)); + return ret; + } + } + + return 0; +} + static void rt5659_calibrate(struct rt5659_priv *rt5659) { int value, count; @@ -4142,14 +4379,9 @@ static int rt5659_i2c_probe(struct i2c_client *i2c, =20 regmap_write(rt5659->regmap, RT5659_RESET, 0); =20 - /* Check if MCLK provided */ - rt5659->mclk =3D devm_clk_get(&i2c->dev, "mclk"); - if (IS_ERR(rt5659->mclk)) { - if (PTR_ERR(rt5659->mclk) !=3D -ENOENT) - return PTR_ERR(rt5659->mclk); - /* Otherwise mark the mclk pointer to NULL */ - rt5659->mclk =3D NULL; - } + ret =3D rt5659_register_clks(&i2c->dev, rt5659); + if (ret) + return ret; =20 rt5659_calibrate(rt5659); =20 diff --git a/sound/soc/codecs/rt5659.h b/sound/soc/codecs/rt5659.h index b49fd8b..d46d39f 100644 --- a/sound/soc/codecs/rt5659.h +++ b/sound/soc/codecs/rt5659.h @@ -1763,6 +1763,7 @@ enum { RT5659_SCLK_S_MCLK, RT5659_SCLK_S_PLL1, RT5659_SCLK_S_RCCLK, + RT5659_NUM_SCLK_SRC_CLKS, }; =20 /* PLL1 Source */ @@ -1772,6 +1773,7 @@ enum { RT5659_PLL1_S_BCLK2, RT5659_PLL1_S_BCLK3, RT5659_PLL1_S_BCLK4, + RT5659_NUM_PLL1_SRC_CLKS, }; =20 enum { @@ -1797,6 +1799,13 @@ struct rt5659_priv { struct gpio_desc *gpiod_reset; struct snd_soc_jack *hs_jack; struct delayed_work jack_detect_work; + + struct clk_hw *clk_sysclk_src; + struct clk_hw *clk_pll_src; + struct clk_hw clk_pll_out; + struct clk *clk_bclk[RT5659_AIFS]; + struct clk *sysclk_ref; + struct clk *pll_ref; struct clk *mclk; =20 int sysclk; --=20 2.7.4 From nobody Tue Jun 23 05:05:44 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AA7BC433F5 for ; Mon, 28 Mar 2022 06:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238374AbiC1GSl (ORCPT ); Mon, 28 Mar 2022 02:18:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238408AbiC1GRv (ORCPT ); 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 06:16:03.0208 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a37d4cff-22ec-4b6c-ba8b-08da10826faf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.234];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT060.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5685 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When Tegra I2S is consumer the clock is driven by the external codec. In such cases, ideally the bit clock (BCLK) rate needs to be updated by provider. Consumer can use standard clock function to get the rate. On Tegra HW it is possible to use I2S BCLK clock as reference to the I/O (other I2S or DMIC or DSPK) interfaces. This input clock is called as SYNC input clock and it can act as a parent clock to any of the remaining I/O interfaces. Thus it is important to set the clock rate in Tegra I2S consumer mode as well. With this patch SYNC input clock rate is updated and any I/O interface relying on this can derive required rate. Signed-off-by: Sameer Pujar --- Following are the DT binding cases I tried on Jetson AGX Xavier platform. 1. Sysclk derived from MCLK : This is currently being used. No DT binding change would be necessary. Clock tree dump snippet in this case with proposed series: ... pll_a | |-- plla_out0 | |-- ahub | |-- aud_mclk | | | |-- rt5659_sysclk | |-- i2s1 ... =20 2. Sysclk is derived from codec internal PLL and this PLL uses I2S bit clock (BCLK) as reference. rt5658: audio-codec@1a { ... clocks =3D <&bpmp TEGRA194_CLK_AUD_MCLK>, <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1>, <&rt5658 0>; clock-names =3D "mclk", "bclk1", "pll_ref", "sysclk"; #clock-cells =3D <1>; clock-output-names =3D "rt5659_pll_out"; ... }; Clock tree dump snippet in this case with proposed series: ... pll_a | |-- plla_out0 | |-- ahub | |-- aud_mclk | |-- i2s1 | |-- rt5659_pll_ref | |-- rt5659_pll_out | |-- rt5659_sysclk ... sound/soc/tegra/tegra210_i2s.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/sound/soc/tegra/tegra210_i2s.c b/sound/soc/tegra/tegra210_i2s.c index 9552bbb..53e5307 100644 --- a/sound/soc/tegra/tegra210_i2s.c +++ b/sound/soc/tegra/tegra210_i2s.c @@ -53,17 +53,24 @@ static int tegra210_i2s_set_clock_rate(struct device *d= ev, =20 regmap_read(i2s->regmap, TEGRA210_I2S_CTRL, &val); =20 - /* No need to set rates if I2S is being operated in slave */ - if (!(val & I2S_CTRL_MASTER_EN)) - return 0; - - err =3D clk_set_rate(i2s->clk_i2s, clock_rate); - if (err) { - dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", - clock_rate, err); - return err; + /* + * If I2S is consumer, then the clock rate is expected to be + * set by the respective provider and thus just read the rate + * in such case. If I2S is provider, then set the clock rate. + */ + if (!(val & I2S_CTRL_MASTER_EN)) { + clock_rate =3D clk_get_rate(i2s->clk_i2s); + } else { + err =3D clk_set_rate(i2s->clk_i2s, clock_rate); + if (err) { + dev_err(dev, "can't set I2S bit clock rate %u, err: %d\n", + clock_rate, err); + return err; + } } =20 + dev_dbg(dev, "bit clock (BCLK) rate is %u\n", clock_rate); + if (!IS_ERR(i2s->clk_sync_input)) { /* * Other I/O modules in AHUB can use i2s bclk as reference --=20 2.7.4