From nobody Mon Jun 22 15:44:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B5A1C433F5 for ; Mon, 21 Mar 2022 12:28:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347338AbiCUMaU (ORCPT ); Mon, 21 Mar 2022 08:30:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347311AbiCUMaO (ORCPT ); Mon, 21 Mar 2022 08:30:14 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 168026418; Mon, 21 Mar 2022 05:28:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1647865729; x=1679401729; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=ml56jHMzZiBNHW/uYlWlw1vcW9YxZvJzFAROWSPNOv8=; b=kfoZ5xbxpCQUu/9L0teU1isyjdLfoddrUeCOMUA3nwTU4EvqrKHPwVs1 Wm/pmc9wIK8T3RpFoU2/WvHndOlUGkLoNtSAR2WaeNjAe68p0wJOIGRwZ nux9KXRq2HljASdd5ib13fI3VeTik+pOJ6z2MhXjM2Bamb54rELENamrH g=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 21 Mar 2022 05:28:48 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg01-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Mar 2022 05:28:48 -0700 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 21 Mar 2022 05:28:48 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 21 Mar 2022 05:28:43 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v5 1/3] arm64: dts: qcom: sc7280: Add nodes for va tx and rx macros and external codecs Date: Mon, 21 Mar 2022 17:58:14 +0530 Message-ID: <1647865696-19192-2-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> References: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SC7280 has VA, TX and RX macros with SoundWire Controllers to attach with codecs like WCD938x, max98360a using soundwire masters and i2s bus. Add these nodes for sc7280 based platforms audio use case. Add tlmm gpio property in wcd938x node for switching CTIA/OMTP Headset. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 6 + arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 8 ++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 172 +++++++++++++++++++++= ++++ 3 files changed, 186 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/= qcom/sc7280-crd.dts index e2efbdd..224a82d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -84,6 +84,12 @@ ap_ts_pen_1v8: &i2c13 { pins =3D "gpio51"; }; =20 +&wcd938x { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&us_euro_select>; + us-euro-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; +}; + &tlmm { tp_int_odl: tp-int-odl { pins =3D "gpio7"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/bo= ot/dts/qcom/sc7280-herobrine.dtsi index de646d9..c6a04c3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -20,6 +20,14 @@ #include "sc7280-chrome-common.dtsi" =20 / { + max98360a: audio-codec-0 { + compatible =3D "maxim,max98360a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&_en>; + sdmode-gpios =3D <&tlmm 63 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; + chosen { stdout-path =3D "serial0:115200n8"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 4a7b18a..5f75c9a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -20,6 +20,41 @@ serial1 =3D &uart7; }; =20 + max98360a: audio-codec-0 { + compatible =3D "maxim,max98360a"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&_en>; + sdmode-gpios =3D <&tlmm 63 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; + + wcd938x: audio-codec-1 { + compatible =3D "qcom,wcd9380-codec"; + #sound-dai-cells =3D <1>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wcd938x_reset_active>, <&wcd938x_reset_sleep>; + reset-gpios =3D <&tlmm 83 GPIO_ACTIVE_HIGH>; + + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + vdd-rxtx-supply =3D <&vreg_l18b_1p8>; + vdd-io-supply =3D <&vreg_l18b_1p8>; + vdd-buck-supply =3D <&vreg_l17b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob>; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 + 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + }; + gpio-keys { compatible =3D "gpio-keys"; label =3D "gpio-keys"; @@ -476,6 +511,143 @@ drive-strength =3D <6>; }; =20 +&soc { + rxmacro: codec@3200000 { + compatible =3D "qcom,sc7280-lpass-rx-macro"; + reg =3D <0 0x03200000 0 0x1000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rx_swr_active>; + + clocks =3D <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&vamacro>; + clock-names =3D "mclk", "npl", "fsgen"; + + power-domains =3D <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names =3D"macro", "dcodec"; + + #clock-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + txmacro: codec@3220000 { + compatible =3D "qcom,sc7280-lpass-tx-macro"; + reg =3D <0 0x03220000 0 0x1000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&tx_swr_active>; + + clocks =3D <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&vamacro>; + clock-names =3D "mclk", "npl", "fsgen"; + + power-domains =3D <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names =3D"macro", "dcodec"; + + #clock-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + vamacro: codec@3370000 { + compatible =3D "qcom,sc7280-lpass-va-macro"; + reg =3D <0 0x03370000 0 0x1000>; + + pinctrl-0 =3D <&dmic01_active>; + pinctrl-names =3D "default"; + + clocks =3D <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; + clock-names =3D "mclk"; + + power-domains =3D <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, + <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + power-domain-names =3D"macro", "dcodec"; + + vdd-micb-supply =3D <&vreg_bob>; + + #clock-cells =3D <0>; + #sound-dai-cells =3D <1>; + }; + + swr0: soundwire@3210000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0 0x03210000 0 0x2000>; + + interrupts =3D ; + clocks =3D <&rxmacro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <0>; + qcom,dout-ports =3D <5>; + + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; + reset-names =3D "swr_audio_cgcr"; + + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; + qcom,ports-sinterval-low =3D /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; + + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + #sound-dai-cells =3D <1>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; + }; + + swr1: soundwire@3230000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0 0x03230000 0 0x2000>; + + interrupts-extended =3D <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "swr_master_irq", "swr_wake_irq"; + clocks =3D <&txmacro>; + clock-names =3D "iface"; + + qcom,din-ports =3D <3>; + qcom,dout-ports =3D <0>; + + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; + reset-names =3D "swr_audio_cgcr"; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x00 0x02>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0x0 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x00 0x01 0x00>; + qcom,port-offset =3D <1>; + + #sound-dai-cells =3D <1>; + #address-cells =3D <2>; + #size-cells =3D <0>; + + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + #sound-dai-cells =3D <1>; + qcom,tx-port-mapping =3D <1 2 3 4>; + }; + }; +}; + &tlmm { amp_en: amp-en { pins =3D "gpio63"; --=20 2.7.4 From nobody Mon Jun 22 15:44:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FCB1C433EF for ; Mon, 21 Mar 2022 12:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347348AbiCUMaY (ORCPT ); Mon, 21 Mar 2022 08:30:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347329AbiCUMaS (ORCPT ); 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Mon, 21 Mar 2022 05:28:52 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 21 Mar 2022 05:28:48 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add lpass cpu node Date: Mon, 21 Mar 2022 17:58:15 +0530 Message-ID: <1647865696-19192-3-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> References: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add lpass cpu node for audio on sc7280 based platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 28 ++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 63 ++++++++++++++++++++++++++++= ++++ 2 files changed, 91 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index 5f75c9a..ca799c2 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -273,6 +273,34 @@ modem-init; }; =20 +&lpass_cpu { + status =3D "okay"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sec_mi2s_data0>, <&sec_mi2s_sclk>, <&sec_mi2s_ws>; + + mi2s-secondary@1 { + reg =3D ; + qcom,playback-sd-lines =3D <0>; + }; + + hdmi-primary@5 { + reg =3D ; + }; + + wcd-rx@6 { + reg =3D ; + }; + + wcd-tx@19 { + reg =3D ; + }; + + va-tx@25 { + reg =3D ; + }; +}; + &pcie1 { status =3D "okay"; perst-gpio =3D <&tlmm 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 499299a..e6ec334 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 / { @@ -1980,6 +1981,68 @@ #clock-cells =3D <1>; }; =20 + lpass_cpu: audio-subsystem@3260000 { + compatible =3D "qcom,sc7280-lpass-cpu"; + + reg =3D <0 0x03987000 0 0x68000>, + <0 0x03b00000 0 0x29000>, + <0 0x03260000 0 0xc000>, + <0 0x03280000 0 0x29000>, + <0 0x03340000 0 0x29000>, + <0 0x0336c000 0 0x3000>; + + reg-names =3D "lpass-hdmiif", + "lpass-lpaif", + "lpass-rxtx-cdc-dma-lpm", + "lpass-rxtx-lpaif", + "lpass-va-lpaif", + "lpass-va-cdc-dma-lpm"; + + iommus =3D <&apps_smmu 0x1820 0>, + <&apps_smmu 0x1821 0>, + <&apps_smmu 0x1832 0>; + status =3D "disabled"; + + power-domains =3D <&rpmhpd SC7280_LCX>; + power-domain-names =3D "lcx"; + required-opps =3D <&rpmhpd_opp_nom>; + + clocks =3D <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_EXT_MCLK0_CLK>, + <&lpasscore LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, + <&lpasscore LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, + <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; + clock-names =3D "aon_cc_audio_hm_h", + "audio_cc_ext_mclk0", + "core_cc_sysnoc_mport_core", + "core_cc_ext_if0_ibit", + "core_cc_ext_if1_ibit", + "audio_cc_codec_mem", + "audio_cc_codec_mem0", + "audio_cc_codec_mem1", + "audio_cc_codec_mem2", + "aon_cc_va_mem0"; + + #sound-dai-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + interrupts =3D , + , + , + ; + + interrupt-names =3D "lpass-irq-lpaif", + "lpass-irq-hdmi", + "lpass-irq-vaif", + "lpass-irq-rxtxif"; + }; + lpass_ag_noc: interconnect@3c40000 { reg =3D <0 0x03c40000 0 0xf080>; compatible =3D "qcom,sc7280-lpass-ag-noc"; --=20 2.7.4 From nobody Mon Jun 22 15:44:33 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 194E9C433EF for ; Mon, 21 Mar 2022 12:29:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245587AbiCUMad (ORCPT ); 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21 Mar 2022 05:28:57 -0700 Received: from nalasex01b.na.qualcomm.com (10.47.209.197) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 21 Mar 2022 05:28:56 -0700 Received: from hu-srivasam-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Mon, 21 Mar 2022 05:28:52 -0700 From: Srinivasa Rao Mandadapu To: , , , , , , , , , , CC: Srinivasa Rao Mandadapu , "Venkata Prasad Potturu" Subject: [PATCH v5 3/3] arm64: dts: qcom: sc7280: Add dt nodes for sound card Date: Mon, 21 Mar 2022 17:58:16 +0530 Message-ID: <1647865696-19192-4-git-send-email-quic_srivasam@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> References: <1647865696-19192-1-git-send-email-quic_srivasam@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt nodes for sound card support, which is using WCD938x headset playback, capture, I2S speaker playback and DMICs via VA macro. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu --- arch/arm64/boot/dts/qcom/sc7280-crd.dts | 8 +++ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 93 ++++++++++++++++++++++++++++= ++++ 2 files changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/= qcom/sc7280-crd.dts index 224a82d..b1b968a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd.dts @@ -90,6 +90,14 @@ ap_ts_pen_1v8: &i2c13 { us-euro-gpios =3D <&tlmm 81 GPIO_ACTIVE_HIGH>; }; =20 +&sound { + audio-routing =3D + "VA DMIC0", "MIC BIAS1", + "VA DMIC1", "MIC BIAS1", + "VA DMIC2", "MIC BIAS3", + "VA DMIC3", "MIC BIAS3"; +}; + &tlmm { tp_int_odl: tp-int-odl { pins =3D "gpio7"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts= /qcom/sc7280-idp.dtsi index ca799c2..369c1e9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -84,6 +84,99 @@ pinctrl-names =3D "default"; pinctrl-0 =3D <&nvme_pwren>; }; + + sound: sound-card { + compatible =3D "google,sc7280-herobrine"; + model =3D "sc7280-wcd938x-max98360a-1mic"; + status =3D "okay"; + audio-routing =3D + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "VA DMIC0", "MIC BIAS3", + "VA DMIC1", "MIC BIAS3", + "VA DMIC2", "MIC BIAS1", + "VA DMIC3", "MIC BIAS1", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT"; + + qcom,msm-mbhc-hphl-swh =3D <1>; + qcom,msm-mbhc-gnd-swh =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + #sound-dai-cells =3D <0>; + + dai-link@1 { + link-name =3D "Secondary MI2S Playback"; + reg =3D ; + cpu { + sound-dai =3D <&lpass_cpu MI2S_SECONDARY>; + }; + + codec { + sound-dai =3D <&max98360a>; + }; + }; + + dai-link@5 { + link-name =3D "DP Playback"; + reg =3D ; + cpu { + sound-dai =3D <&lpass_cpu LPASS_DP_RX>; + }; + + codec { + sound-dai =3D <&mdss_dp>; + }; + }; + + dai-link@6 { + link-name =3D "WCD Playback"; + reg =3D ; + cpu { + sound-dai =3D <&lpass_cpu LPASS_CDC_DMA_RX0>; + }; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr0 0>, <&rxmacro 0>; + }; + }; + + dai-link@19 { + link-name =3D "WCD Capture"; + reg =3D ; + cpu { + sound-dai =3D <&lpass_cpu LPASS_CDC_DMA_TX3>; + }; + + codec { + sound-dai =3D <&wcd938x 1>, <&swr1 0>, <&txmacro 0>; + }; + }; + + dai-link@25 { + link-name =3D "DMIC Capture"; + reg =3D ; + cpu { + sound-dai =3D <&lpass_cpu LPASS_CDC_DMA_VA_TX0>; + }; + + codec { + sound-dai =3D <&vamacro 0>; + }; + }; + }; }; =20 &apps_rsc { --=20 2.7.4