From nobody Sun Sep 22 05:36:12 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B226C433F5 for ; Thu, 17 Mar 2022 07:54:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230430AbiCQHzP (ORCPT ); Thu, 17 Mar 2022 03:55:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44266 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230404AbiCQHzG (ORCPT ); Thu, 17 Mar 2022 03:55:06 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73886DAFFC for ; Thu, 17 Mar 2022 00:53:47 -0700 (PDT) X-UUID: 23418766904b4171aa9a462e1781642b-20220317 X-UUID: 23418766904b4171aa9a462e1781642b-20220317 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 126323856; Thu, 17 Mar 2022 15:53:42 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 17 Mar 2022 15:53:42 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 15:53:41 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Mar 2022 15:53:40 +0800 From: To: , , , , CC: , , , , , , , Xinlei Lee Subject: [PATCH v3,3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer Date: Thu, 17 Mar 2022 15:53:30 +0800 Message-ID: <1647503611-13144-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1647503611-13144-1-git-send-email-xinlei.lee@mediatek.com> References: <1647503611-13144-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitao Shi To comply with the panel sequence, hold the mipi signal to LP00 before the = dcs cmds transmission, and pull the mipi signal high from LP00 to LP11 until the start of the dcs = cmds transmission. If dsi is not in cmd mode, then dsi will pull the mipi signal high in the m= tk_output_dsi_enable function. Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge API") Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dsi.c | 31 +++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index e33caaca11a7..b509d59235e2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -203,6 +203,7 @@ struct mtk_dsi { struct mtk_phy_timing phy_timing; int refcount; bool enabled; + bool lanes_ready; u32 irq_data; wait_queue_head_t irq_wait_queue; const struct mtk_dsi_driver_data *driver_data; @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); =20 - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); - mtk_dsi_clk_ulp_mode_leave(dsi); - mtk_dsi_lane0_ulp_mode_leave(dsi); - mtk_dsi_clk_hs_mode(dsi, 0); - return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk); @@ -689,6 +683,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) clk_disable_unprepare(dsi->digital_clk); =20 phy_power_off(dsi->phy); + + dsi->lanes_ready =3D false; } =20 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) @@ -696,6 +692,16 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; =20 + if (!dsi->lanes_ready) { + dsi->lanes_ready =3D true; + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); + mtk_dsi_clk_ulp_mode_leave(dsi); + mtk_dsi_lane0_ulp_mode_leave(dsi); + mtk_dsi_clk_hs_mode(dsi, 0); + } + mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); =20 @@ -995,6 +1001,17 @@ static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_= host *host, if (MTK_DSI_HOST_IS_READ(msg->type)) irq_flag |=3D LPRX_RD_RDY_INT_FLAG; =20 + if (!dsi->lanes_ready) { + dsi->lanes_ready =3D true; + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); + mtk_dsi_clk_ulp_mode_leave(dsi); + mtk_dsi_lane0_ulp_mode_leave(dsi); + mtk_dsi_clk_hs_mode(dsi, 0); + msleep(20); + } + ret =3D mtk_dsi_host_send_cmd(dsi, msg, irq_flag); if (ret) goto restore_dsi_mode; --=20 2.18.0