From nobody Tue Jun 23 08:14:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D764C433F5 for ; Tue, 8 Mar 2022 16:57:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348097AbiCHQ6Y (ORCPT ); Tue, 8 Mar 2022 11:58:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243534AbiCHQ5p (ORCPT ); Tue, 8 Mar 2022 11:57:45 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 536F352B2A for ; Tue, 8 Mar 2022 08:56:48 -0800 (PST) Date: Tue, 08 Mar 2022 16:56:46 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1646758607; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=sc/+FuQv3bGeB9ZDvrmW3VP9TSQijY8TnMjLCGiLDB0=; b=TxTckkvAnP3gJ0UkIGXI6yK7yBMAB4Lx2JNA8WaEusoK3kG1FC/zseBwERvXByep37uR6h QGNg+Jzxy77Uks7oamAqk6/Aa7vpBG9d6vUJ0FQrEuVWA5Ucz5s5Jc4T/xEUKAxFtj45MD fg+UyGhLZiyqdqmuKNymOosSmaC4qkHvnJd9DY3KYc6iddibdNh5Zx6p+t9bZi2C1dqDgH qjykjajOPKTWZMHa0wUG16Ge979ncYJFMgITiV9YtagkhnUa2rHSt6gK7pO1vIqM/kaNAx qDbV9ZUMVITgLpxuRTDaVJfFoMkpS337edYCAyzrvAfO0sBd+Z/4yKwP9868hg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1646758607; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=sc/+FuQv3bGeB9ZDvrmW3VP9TSQijY8TnMjLCGiLDB0=; b=MHhrlTHIk4cO34dnEhz7KQTeWsGZGnYQN+8U2MDTDv1d2xuwgWunySUMklKZI689xYr9+/ qpAHTRNCfBcggIBg== From: "irqchip-bot for Marc Zyngier" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Cc: Rob Herring , Hector Martin , Marc Zyngier , tglx@linutronix.de MIME-Version: 1.0 Message-ID: <164675860602.16921.1205276128705301674.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 74703b13f9d2ef286ef588f29295a2fd30b5f295 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/74703b13f9d2ef286ef588f29295a2fd30b5f295 Author: Marc Zyngier AuthorDate: Mon, 01 Nov 2021 19:58:42=20 Committer: Marc Zyngier CommitterDate: Mon, 07 Feb 2022 16:00:41=20 dt-bindings: apple,aic: Add CPU PMU per-cpu pseudo-interrupts Advertise the two pseudo-interrupts that tied to the two PMU flavours present in the Apple M1 SoC. We choose the expose two different pseudo-interrupts to the OS as the e-core PMU is obviously different from the p-core one, effectively presenting two different devices. Acked-by: Rob Herring Reviewed-by: Hector Martin Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml | 2 = ++ include/dt-bindings/interrupt-controller/apple-aic.h | 2 = ++ 2 files changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,a= ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.= yaml index 9735902..c7577d4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml @@ -56,6 +56,8 @@ properties: - 1: virtual HV timer - 2: physical guest timer - 3: virtual guest timer + - 4: 'efficient' CPU PMU + - 5: 'performance' CPU PMU =20 The 3rd cell contains the interrupt flags. This is normally IRQ_TYPE_LEVEL_HIGH (4). diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include= /dt-bindings/interrupt-controller/apple-aic.h index 604f2bb..bf3aac0 100644 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ b/include/dt-bindings/interrupt-controller/apple-aic.h @@ -11,5 +11,7 @@ #define AIC_TMR_HV_VIRT 1 #define AIC_TMR_GUEST_PHYS 2 #define AIC_TMR_GUEST_VIRT 3 +#define AIC_CPU_PMU_E 4 +#define AIC_CPU_PMU_P 5 =20 #endif