From nobody Sun Sep 22 07:27:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB309C433F5 for ; Fri, 4 Mar 2022 10:16:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234069AbiCDKRI (ORCPT ); Fri, 4 Mar 2022 05:17:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232140AbiCDKQ5 (ORCPT ); Fri, 4 Mar 2022 05:16:57 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3270F1A06DA for ; Fri, 4 Mar 2022 02:16:09 -0800 (PST) X-UUID: 4deb768d8428441ea6fdc307b9fe0b41-20220304 X-UUID: 4deb768d8428441ea6fdc307b9fe0b41-20220304 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 510925633; Fri, 04 Mar 2022 18:16:04 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 18:16:02 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 4 Mar 2022 18:16:01 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 4 Mar 2022 18:16:00 +0800 From: To: , , , , CC: , , , , , , , , Xinlei Lee Subject: [PATCH v2,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 Date: Fri, 4 Mar 2022 18:15:53 +0800 Message-ID: <1646388956-8033-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1646388956-8033-1-git-send-email-xinlei.lee@mediatek.com> References: <1646388956-8033-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitao Shi Old sequence: 1. Pull the MIPI signal high 2. Delay & Dsi_reset 3. Set the dsi timing register 4. dsi clk & lanes leave ulp mode and enter hs mode New sequence: 1. Set the dsi timing register 2. Pull the MIPI signal high 3. Delay & Dsi_reset 4. dsi clk & lanes leave ulp mode and enter hs mode In the new sequence 2 & 3 & 4 will be moved to dsi_enbale in later patch. Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 5d90d2eb0019..6d7b66d5da42 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); =20 - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); mtk_dsi_ps_control_vact(dsi); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); =20 + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); --=20 2.18.0