From nobody Tue Jun 23 16:15:38 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02F59C433EF for ; Wed, 2 Mar 2022 13:40:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242301AbiCBNlj (ORCPT ); Wed, 2 Mar 2022 08:41:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242297AbiCBNlh (ORCPT ); Wed, 2 Mar 2022 08:41:37 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF7FE36E1F for ; Wed, 2 Mar 2022 05:40:54 -0800 (PST) Date: Wed, 02 Mar 2022 13:40:51 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1646228452; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LLGQ/WL/ftFkeXT1z6e2kqcR2dMs3LwyBbuotjCoh5U=; b=nyMkSewkJnZP8ztqzWaX6P/aHFFY+JLPLLbwe9ayV3/+n2uy1/G1je1L95lTyRPaSnaLjq OxfoIE/lsIxC/HDl9NdwXGO6zDVsyQDgr42qxVvoxDj23ShBZ2kLqAaR/sofUINLqY/THN UES8ps6PW6rUiZYB78gHClA7Zu4ON3mrhYG9ffTeMou3x7Wa0fQ36nxqZaj3emwu4UpLiM 2peqouhPDZuCePNnOBz2zncyK3aNkjVQ33oDBSVRdDFLuc+ZtAukWksqzw9Wmomlr0cgnu uQBY+ROSRfkCRu8/XCM9sSxlMeQmL7EnBz0bdarHzKIJF4o/IN9LlylGB8n7Vg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1646228452; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LLGQ/WL/ftFkeXT1z6e2kqcR2dMs3LwyBbuotjCoh5U=; b=W0vSlduBbDgR/emPCqR/CGdPZEuzAc8LETQyQdP51hShnSueokVOHbGYJIR0HwXmORLTt4 eYHjUWDHUUt+6pBw== From: "irqchip-bot for Niklas Cassel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode Cc: Niklas Cassel , Anup Patel , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220302131544.3166154-3-Niklas.Cassel@wdc.com> References: <20220302131544.3166154-3-Niklas.Cassel@wdc.com> MIME-Version: 1.0 Message-ID: <164622845144.16921.18355558429149902686.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 098fdbc3531f06aae2426b3a6f9bd730e7691258 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/098fdbc3531f06aae2426b3a6f9bd730e7691258 Author: Niklas Cassel AuthorDate: Wed, 02 Mar 2022 13:15:53=20 Committer: Marc Zyngier CommitterDate: Wed, 02 Mar 2022 13:30:50=20 irqchip/sifive-plic: Disable S-mode IRQs if running in M-mode When detecting a context for a privilege mode different from the current running privilege mode, we simply skip to the next context register. This means that we never clear the S-mode enable bits when running in M-mode. On canaan k210, a bunch of S-mode interrupts are enabled by the bootrom. These S-mode specific interrupts should never trigger, since we never set the mie.SEIE bit in the parent interrupt controller (riscv-intc). However, we will be able to see the mip.SEIE bit set as pending. This isn't a good default when CONFIG_RISCV_M_MODE is set, since in that case we will never enter a lower privilege mode (e.g. S-mode). Let's clear the S-mode enable bits when running the kernel in M-mode, such that we won't have a interrupt pending bit set, which we will never clear. Signed-off-by: Niklas Cassel Reviewed-by: Anup Patel Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220302131544.3166154-3-Niklas.Cassel@wdc.= com --- drivers/irqchip/irq-sifive-plic.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index 28b86cd..7ae12e5 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -81,17 +81,21 @@ static int plic_parent_irq __ro_after_init; static bool plic_cpuhp_setup_done __ro_after_init; static DEFINE_PER_CPU(struct plic_handler, plic_handlers); =20 -static inline void plic_toggle(struct plic_handler *handler, - int hwirq, int enable) +static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) { - u32 __iomem *reg =3D handler->enable_base + (hwirq / 32) * sizeof(u32); + u32 __iomem *reg =3D enable_base + (hwirq / 32) * sizeof(u32); u32 hwirq_mask =3D 1 << (hwirq % 32); =20 - raw_spin_lock(&handler->enable_lock); if (enable) writel(readl(reg) | hwirq_mask, reg); else writel(readl(reg) & ~hwirq_mask, reg); +} + +static void plic_toggle(struct plic_handler *handler, int hwirq, int enabl= e) +{ + raw_spin_lock(&handler->enable_lock); + __plic_toggle(handler->enable_base, hwirq, enable); raw_spin_unlock(&handler->enable_lock); } =20 @@ -324,8 +328,18 @@ static int __init plic_init(struct device_node *node, * Skip contexts other than external interrupts for our * privilege level. */ - if (parent.args[0] !=3D RV_IRQ_EXT) + if (parent.args[0] !=3D RV_IRQ_EXT) { + /* Disable S-mode enable bits if running in M-mode. */ + if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { + void __iomem *enable_base =3D priv->regs + + CONTEXT_ENABLE_BASE + + i * CONTEXT_ENABLE_SIZE; + + for (hwirq =3D 1; hwirq <=3D nr_irqs; hwirq++) + __plic_toggle(enable_base, hwirq, 0); + } continue; + } =20 hartid =3D riscv_of_parent_hartid(parent.np); if (hartid < 0) {