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Wed, 2 Mar 2022 00:44:01 -0800 From: Ashish Mhetre To: , , , , , , , CC: , , Subject: [Patch v4 1/4] arm64: tegra: Add memory controller channels Date: Wed, 2 Mar 2022 14:13:26 +0530 Message-ID: <1646210609-21943-2-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> References: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 0932f8d7-6848-4d53-519a-08d9fc28d01c X-MS-TrafficTypeDiagnostic: BN9PR12MB5034:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Ua+9wnIESBkiBj1U3y8tZOB7aRcoGGtBLzKko2xfAPNA4mT7F8P6cHd5Dv93/5/H0FmF8tjvFWNjybBDde3iuTg9ddZM9xZ1oQAvo7croAcefEiZlL1oRr7GnqtbVxIW53XQiXkQTYAXnO8nCd7RVsA5+oBcbnGYS74+sRIzjFcHjFr6gqNj27RXcyBfBmsd0weRPgDwsJbOrZLsYcoQt8rJfXjLW1XO+d5TO8thve9RchL8JF8TSnmvhohvAcH50U0axzWUXADBsG2WR47sdswIbM+wCo22Md2BN0ku6OQZ7OR1kwfcYjMtySOGWdFLV+uBsLRZnEGMZ/PNGe5ZfZOjS+ijx9E0ltg0eFsvn/QkIUNYnlutfr1SYImLU2um2yYwCpfWsUmUPuf5HzBUiSaPNYiePMEiEwWSaEBeq89zMYLt/J/6o5gRg5kwSiVWtzvG59fQJwdOftf7ZCUTeE4JFcNIds8RlanAemzUlWEDwNsRTVQs7Yuz5vFeK+nwWoSDyxa78mEobax/Mrq0+9DR1iAU8mkKAndidWpszLoRQvTEkHKa4XtFiuhOK+TF67mlRcZxABnPguxBgbPYClxXhwxHuMGwflmNyqRHVlDnJ6lFdPH0bDacNlhxmGBbX+MPwQeWAAsOCGtjlYMN/riegOZMWCxHTFXXcS4qvokuRPyIbBeogPl+sUXaMGUAR5nGEsICjRR6shfz5OWp6g== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(186003)(26005)(107886003)(426003)(336012)(40460700003)(7696005)(2906002)(2616005)(82310400004)(86362001)(36860700001)(83380400001)(47076005)(356005)(81166007)(54906003)(6666004)(5660300002)(4326008)(70206006)(8936002)(508600001)(36756003)(8676002)(70586007)(110136005)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:06.8950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0932f8d7-6848-4d53-519a-08d9fc28d01c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5034 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Signed-off-by: Ashish Mhetre --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 ++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 21 ++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 21 ++++++++++++++++++--- 3 files changed, 42 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts= /nvidia/tegra186.dtsi index e9b40f5..9c14404 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -521,7 +521,12 @@ =20 mc: memory-controller@2c00000 { compatible =3D "nvidia,tegra186-mc"; - reg =3D <0x0 0x02c00000 0x0 0xb0000>; + reg =3D <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ interrupts =3D ; status =3D "disabled"; =20 diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index c28bf4d..e19c56c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -604,9 +604,24 @@ =20 mc: memory-controller@2c00000 { compatible =3D "nvidia,tegra194-mc"; - reg =3D <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg =3D <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ interrupts =3D ; #interconnect-cells =3D <1>; status =3D "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index aaace60..6e33d2b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -507,9 +507,24 @@ =20 mc: memory-controller@2c00000 { compatible =3D "nvidia,tegra234-mc"; - reg =3D <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg =3D <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ interrupts =3D ; #interconnect-cells =3D <1>; status =3D "okay"; --=20 2.7.4 From nobody Tue Jun 23 16:12:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F459C433F5 for ; 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Wed, 2 Mar 2022 00:44:10 -0800 From: Ashish Mhetre To: , , , , , , , CC: , , Subject: [Patch v4 2/4] dt-bindings: memory: Update reg maxitems for tegra186 Date: Wed, 2 Mar 2022 14:13:27 +0530 Message-ID: <1646210609-21943-3-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> References: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8d127c84-ec95-4872-523d-08d9fc28d5ba X-MS-TrafficTypeDiagnostic: SJ0PR12MB5424:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eGgLfOl0ROVVd75hzYPsy34e5tF3AdOQPz7xdXfx7kC2Z1dg2z9N9BS6Xs5PI8PGnCsd6x6CYZl2MFCmK0pfgTjIRMHyZ5VujqEy4WqLhBgHf9ij0iGdQEVQHrgwyNcpMVxlaYh9eoHi/cOdGB2De4CoOFnw9ATqi+wY2aK5WIo6xBjGe8hdv1Q4MH4GntlurhJi+yqeULbr4G1jH/1KZnvs5DNro8+1ZUxS2JCxU3SlOaaifpvp8KcirQNO/ZB95G8vYxa7AUH6/SM/umonMdp7/ZgbZP4kTGgrPbHlKWWZ1XvqyzZUJ6ZQfZzb83aQTaCIE7a7qu5EvDVcHpYlLPeMOLMMsP3uTPZ6SQTn4wF6yYqsw/3bBbubdvXnEkFdFjiDW0cHWLlUipo5UojOdijgP3ryU7/X6lj4XYJa04fwIMsm7XZ6oL0rx3qA2ovDcvBFo2AmtHkk8BkuojoQ+f1sqch3i6ALwBThFBpKQYsI9Yv/0AOIzpfKImiqKD9AlU7K6GL8iwu6PX6vWv9RLOQzvPHAlIzXb3GtekxUf9+hbRE+noio5c8IQrV5TZuWOWttAHvD4wy7/wHH53lMeMq3QbRADjTBT3kJEHcwRBZh4ZE3zvWVA3L7Wq7yxFdJcBWV/ZAyUEsNFdFjhD4Ck6Hk58cSHJp7mwTdLSi4XJDAaqyeFGCwm51d8aerZB+m7VkoubWJpAObJfyqJ9rEuQ== X-Forefront-Antispam-Report: CIP:12.22.5.238;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:mail.nvidia.com;PTR:InfoNoRecords;CAT:NONE;SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(47076005)(40460700003)(508600001)(36860700001)(107886003)(110136005)(54906003)(8936002)(86362001)(5660300002)(15650500001)(81166007)(356005)(4326008)(82310400004)(316002)(8676002)(36756003)(83380400001)(26005)(186003)(336012)(2616005)(426003)(2906002)(70586007)(70206006)(6666004)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:16.3191 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d127c84-ec95-4872-523d-08d9fc28d5ba X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5424 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From tegra186 onwards, memory controller support multiple channels. Reg items are updated with address and size of these channels. Tegra186 has overall 5 memory controller channels. Tegra194 and tegra234 have overall 17 memory controller channels each. There is 1 reg item for memory controller stream-id registers. So update the reg maxItems to 18 in tegra186 devicetree documentation. Signed-off-by: Ashish Mhetre --- .../devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml | = 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidi= a,tegra186-mc.yaml index 13c4c82..eb7ed00 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml @@ -35,7 +35,7 @@ properties: =20 reg: minItems: 1 - maxItems: 3 + maxItems: 18 =20 interrupts: items: --=20 2.7.4 From nobody Tue Jun 23 16:12:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB83C43219 for ; Wed, 2 Mar 2022 08:44:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240198AbiCBIpX (ORCPT ); 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Wed, 2 Mar 2022 08:44:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.9; Wed, 2 Mar 2022 00:44:24 -0800 Received: from amhetre.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.986.9 via Frontend Transport; Wed, 2 Mar 2022 00:44:20 -0800 From: Ashish Mhetre To: , , , , , , , CC: , , Subject: [Patch v4 3/4] memory: tegra: Add memory controller channels support Date: Wed, 2 Mar 2022 14:13:28 +0530 Message-ID: <1646210609-21943-4-git-send-email-amhetre@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> References: <1646210609-21943-1-git-send-email-amhetre@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6c7c4b1a-7f4f-454a-9585-08d9fc28dbc8 X-MS-TrafficTypeDiagnostic: BN8PR12MB3249:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:26.4633 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c7c4b1a-7f4f-454a-9585-08d9fc28dbc8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.238];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT055.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3249 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From tegra186 onwards, memory controller support multiple channels. Add support for mapping address spaces of these channels. During error interrupts from memory controller, appropriate registers from these channels need to be accessed for logging error info. Signed-off-by: Ashish Mhetre --- drivers/memory/tegra/mc.c | 6 ++++++ drivers/memory/tegra/tegra186.c | 21 +++++++++++++++++++++ drivers/memory/tegra/tegra194.c | 1 + drivers/memory/tegra/tegra234.c | 1 + include/soc/tegra/mc.h | 7 +++++++ 5 files changed, 36 insertions(+) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index bf3abb6..3cda1d9 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -749,6 +749,12 @@ static int tegra_mc_probe(struct platform_device *pdev) if (IS_ERR(mc->regs)) return PTR_ERR(mc->regs); =20 + if (mc->soc->ops && mc->soc->ops->map_regs) { + err =3D mc->soc->ops->map_regs(mc, pdev); + if (err < 0) + return err; + } + mc->debugfs.root =3D debugfs_create_dir("mc", NULL); =20 if (mc->soc->ops && mc->soc->ops->probe) { diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 3d15388..59a4425 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -139,11 +139,31 @@ static int tegra186_mc_probe_device(struct tegra_mc *= mc, struct device *dev) return 0; } =20 +static int tegra186_mc_map_regs(struct tegra_mc *mc, + struct platform_device *pdev) +{ + struct resource *res; + int i; + + mc->mcb_regs =3D devm_platform_get_and_ioremap_resource(pdev, 1, &res); + if (IS_ERR(mc->mcb_regs)) + return PTR_ERR(mc->mcb_regs); + + for (i =3D 0; i < mc->soc->num_channels; i++) { + mc->mc_regs[i] =3D devm_platform_get_and_ioremap_resource(pdev, i + 2, &= res); + if (IS_ERR(mc->mc_regs[i])) + return PTR_ERR(mc->mc_regs[i]); + } + + return 0; +} + const struct tegra_mc_ops tegra186_mc_ops =3D { .probe =3D tegra186_mc_probe, .remove =3D tegra186_mc_remove, .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, + .map_regs =3D tegra186_mc_map_regs, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -875,6 +895,7 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra186_mc_clients), .clients =3D tegra186_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 4, .ops =3D &tegra186_mc_ops, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index cab998b..9400117 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1347,5 +1347,6 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra194_mc_clients), .clients =3D tegra194_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 16, .ops =3D &tegra186_mc_ops, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index e22824a..6335a13 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -97,5 +97,6 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra234_mc_clients), .clients =3D tegra234_mc_clients, .num_address_bits =3D 40, + .num_channels =3D 16, .ops =3D &tegra186_mc_ops, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1066b11..92f810c 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -13,6 +13,9 @@ #include #include #include +#include + +#define MC_MAX_CHANNELS 16 =20 struct clk; struct device; @@ -181,6 +184,7 @@ struct tegra_mc_ops { int (*resume)(struct tegra_mc *mc); irqreturn_t (*handle_irq)(int irq, void *data); int (*probe_device)(struct tegra_mc *mc, struct device *dev); + int (*map_regs)(struct tegra_mc *mc, struct platform_device *pdev); }; =20 struct tegra_mc_soc { @@ -194,6 +198,7 @@ struct tegra_mc_soc { unsigned int atom_size; =20 u8 client_id_mask; + u8 num_channels; =20 const struct tegra_smmu_soc *smmu; =20 @@ -212,6 +217,8 @@ struct tegra_mc { struct tegra_smmu *smmu; struct gart_device *gart; void __iomem *regs; + void __iomem *mcb_regs; + void __iomem *mc_regs[MC_MAX_CHANNELS]; struct clk *clk; int irq; =20 --=20 2.7.4 From nobody Tue Jun 23 16:12:48 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2617EC433F5 for ; Wed, 2 Mar 2022 08:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240200AbiCBIp2 (ORCPT ); Wed, 2 Mar 2022 03:45:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240044AbiCBIpS (ORCPT ); Wed, 2 Mar 2022 03:45:18 -0500 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2080.outbound.protection.outlook.com [40.107.223.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9608DBAB9D; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2022 08:44:32.3760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 45e5324d-1943-47da-8d51-08d9fc28df5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[12.22.5.235];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2402 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add new function 'get_int_channel' in tegra_mc_soc struture which is implemented by tegra SOCs which support multiple MC channels. This function returns the channel which should be used to get the information of interrupts. Remove static from tegra30_mc_handle_irq and use it as interrupt handler for MC interrupts on tegra186, tegra194 and tegra234 to log the errors. Add error specific MC status and address register bits and use them on tegra186, tegra194 and tegra234. Add error logging for generalized carveout interrupt on tegra186, tegra194 and tegra234. Add error logging for route sanity interrupt on tegra194 an tegra234. Add register for higher bits of error address which is available on tegra194 and tegra234. Add a boolean variable 'has_addr_hi_reg' in tegra_mc_soc struture which will be true if soc has register for higher bits of memory controller error address. Set it true for tegra194 and tegra234. Signed-off-by: Ashish Mhetre Reported-by: Dan Carpenter Reported-by: kernel test robot --- drivers/memory/tegra/mc.c | 102 ++++++++++++++++++++++++++++++++++--= ---- drivers/memory/tegra/mc.h | 37 ++++++++++++++- drivers/memory/tegra/tegra186.c | 45 ++++++++++++++++++ drivers/memory/tegra/tegra194.c | 44 +++++++++++++++++ drivers/memory/tegra/tegra234.c | 59 +++++++++++++++++++++++ include/soc/tegra/mc.h | 4 ++ 6 files changed, 275 insertions(+), 16 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 3cda1d9..bb861a8 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -508,14 +508,32 @@ int tegra30_mc_probe(struct tegra_mc *mc) return 0; } =20 -static irqreturn_t tegra30_mc_handle_irq(int irq, void *data) +const struct tegra_mc_ops tegra30_mc_ops =3D { + .probe =3D tegra30_mc_probe, + .handle_irq =3D tegra30_mc_handle_irq, +}; +#endif + +irqreturn_t tegra30_mc_handle_irq(int irq, void *data) { struct tegra_mc *mc =3D data; unsigned long status; unsigned int bit; + int channel; + + if (mc->soc->num_channels && mc->soc->get_int_channel) { + int err; + + err =3D mc->soc->get_int_channel(mc, &channel); + if (err < 0) + return IRQ_NONE; + + /* mask all interrupts to avoid flooding */ + status =3D mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask; + } else { + status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; + } =20 - /* mask all interrupts to avoid flooding */ - status =3D mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask; if (!status) return IRQ_NONE; =20 @@ -523,18 +541,66 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, voi= d *data) const char *error =3D tegra_mc_status_names[bit] ?: "unknown"; const char *client =3D "unknown", *desc; const char *direction, *secure; + u32 status_reg, addr_reg; + u32 intmask =3D BIT(bit); phys_addr_t addr =3D 0; +#ifdef CONFIG_PHYS_ADDR_T_64BIT + u32 addr_hi_reg =3D 0; +#endif unsigned int i; char perm[7]; u8 id, type; u32 value; =20 - value =3D mc_readl(mc, MC_ERR_STATUS); + switch (intmask) { + case MC_INT_DECERR_VPR: + status_reg =3D MC_ERR_VPR_STATUS; + addr_reg =3D MC_ERR_VPR_ADR; + break; + + case MC_INT_SECERR_SEC: + status_reg =3D MC_ERR_SEC_STATUS; + addr_reg =3D MC_ERR_SEC_ADR; + break; + + case MC_INT_DECERR_MTS: + status_reg =3D MC_ERR_MTS_STATUS; + addr_reg =3D MC_ERR_MTS_ADR; + break; + + case MC_INT_DECERR_GENERALIZED_CARVEOUT: + status_reg =3D MC_ERR_GENERALIZED_CARVEOUT_STATUS; + addr_reg =3D MC_ERR_GENERALIZED_CARVEOUT_ADR; + break; + + case MC_INT_DECERR_ROUTE_SANITY: + status_reg =3D MC_ERR_ROUTE_SANITY_STATUS; + addr_reg =3D MC_ERR_ROUTE_SANITY_ADR; + break; + + default: + status_reg =3D MC_ERR_STATUS; + addr_reg =3D MC_ERR_ADR; + +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if (mc->soc->has_addr_hi_reg) + addr_hi_reg =3D MC_ERR_ADR_HI; +#endif + break; + } + + if (mc->soc->num_channels) + value =3D mc_ch_readl(mc, channel, status_reg); + else + value =3D mc_readl(mc, status_reg); =20 #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->num_address_bits > 32) { - addr =3D ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & - MC_ERR_STATUS_ADR_HI_MASK); + if (addr_hi_reg) + addr =3D mc_ch_readl(mc, channel, addr_hi_reg); + else + addr =3D ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & + MC_ERR_STATUS_ADR_HI_MASK); addr <<=3D 32; } #endif @@ -591,7 +657,10 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, void= *data) break; } =20 - value =3D mc_readl(mc, MC_ERR_ADR); + if (mc->soc->num_channels) + value =3D mc_ch_readl(mc, channel, addr_reg); + else + value =3D mc_readl(mc, addr_reg); addr |=3D value; =20 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", @@ -600,17 +669,14 @@ static irqreturn_t tegra30_mc_handle_irq(int irq, voi= d *data) } =20 /* clear interrupts */ - mc_writel(mc, status, MC_INTSTATUS); + if (mc->soc->num_channels) + mc_ch_writel(mc, channel, status, MC_INTSTATUS); + else + mc_writel(mc, status, MC_INTSTATUS); =20 return IRQ_HANDLED; } =20 -const struct tegra_mc_ops tegra30_mc_ops =3D { - .probe =3D tegra30_mc_probe, - .handle_irq =3D tegra30_mc_handle_irq, -}; -#endif - const char *const tegra_mc_status_names[32] =3D { [ 1] =3D "External interrupt", [ 6] =3D "EMEM address decode error", @@ -622,6 +688,8 @@ const char *const tegra_mc_status_names[32] =3D { [12] =3D "VPR violation", [13] =3D "Secure carveout violation", [16] =3D "MTS carveout violation", + [17] =3D "Generalized carveout violation", + [20] =3D "Route Sanity error", }; =20 const char *const tegra_mc_error_names[8] =3D { @@ -770,7 +838,11 @@ static int tegra_mc_probe(struct platform_device *pdev) =20 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); =20 - mc_writel(mc, mc->soc->intmask, MC_INTMASK); + if (mc->soc->num_channels) + mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask, + MC_INTMASK); + else + mc_writel(mc, mc->soc->intmask, MC_INTMASK); =20 err =3D devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, = 0, dev_name(&pdev->dev), mc); diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 062886e..3836c35 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -43,7 +43,21 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc - +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_ERR_ADR_HI 0x11fc + +#define MC_INT_DECERR_ROUTE_SANITY BIT(20) +#define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) #define MC_INT_DECERR_MTS BIT(16) #define MC_INT_SECERR_SEC BIT(13) #define MC_INT_DECERR_VPR BIT(12) @@ -78,6 +92,8 @@ =20 #define MC_TIMING_UPDATE BIT(0) =20 +#define MC_BROADCAST_CHANNEL ~0 + static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) { val =3D val * percents; @@ -92,6 +108,24 @@ icc_provider_to_tegra_mc(struct icc_provider *provider) return container_of(provider, struct tegra_mc, provider); } =20 +static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, + unsigned long offset) +{ + if (ch =3D=3D MC_BROADCAST_CHANNEL) + return readl_relaxed(mc->mcb_regs + offset); + + return readl_relaxed(mc->mc_regs[ch] + offset); +} + +static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, + u32 value, unsigned long offset) +{ + if (ch =3D=3D MC_BROADCAST_CHANNEL) + writel_relaxed(value, mc->mcb_regs + offset); + else + writel_relaxed(value, mc->mc_regs[ch] + offset); +} + static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -156,6 +190,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops; extern const struct tegra_mc_ops tegra186_mc_ops; #endif =20 +irqreturn_t tegra30_mc_handle_irq(int irq, void *data); extern const char * const tegra_mc_status_names[32]; extern const char * const tegra_mc_error_names[8]; =20 diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index 59a4425..bce0237 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -16,6 +16,8 @@ #include #endif =20 +#include "mc.h" + #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) @@ -164,6 +166,7 @@ const struct tegra_mc_ops tegra186_mc_ops =3D { .resume =3D tegra186_mc_resume, .probe_device =3D tegra186_mc_probe_device, .map_regs =3D tegra186_mc_map_regs, + .handle_irq =3D tegra30_mc_handle_irq, }; =20 #if defined(CONFIG_ARCH_TEGRA_186_SOC) @@ -891,11 +894,53 @@ static const struct tegra_mc_client tegra186_mc_clien= ts[] =3D { }, }; =20 +static int tegra186_mc_get_channel(struct tegra_mc *mc, int *mc_channel) +{ + u32 g_intstatus; + + g_intstatus =3D mc_ch_readl(mc, MC_BROADCAST_CHANNEL, + MC_GLOBAL_INTSTATUS); + + switch (g_intstatus & mc->soc->int_channel_mask) { + case BIT(0): + *mc_channel =3D 0; + break; + + case BIT(1): + *mc_channel =3D 1; + break; + + case BIT(2): + *mc_channel =3D 2; + break; + + case BIT(3): + *mc_channel =3D 3; + break; + + case BIT(24): + *mc_channel =3D MC_BROADCAST_CHANNEL; + break; + + default: + pr_err("Unknown interrupt source\n"); + return -EINVAL; + } + + return 0; +} + const struct tegra_mc_soc tegra186_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra186_mc_clients), .clients =3D tegra186_mc_clients, .num_address_bits =3D 40, .num_channels =3D 4, + .client_id_mask =3D 0xff, + .intmask =3D MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, .ops =3D &tegra186_mc_ops, + .int_channel_mask =3D 0x100000f, + .get_int_channel =3D tegra186_mc_get_channel, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 9400117..bc16567 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1343,10 +1343,54 @@ static const struct tegra_mc_client tegra194_mc_cli= ents[] =3D { }, }; =20 +static int tegra194_mc_get_channel(struct tegra_mc *mc, int *mc_channel) +{ + u32 g_intstatus; + + g_intstatus =3D mc_ch_readl(mc, MC_BROADCAST_CHANNEL, + MC_GLOBAL_INTSTATUS); + + switch (g_intstatus & mc->soc->int_channel_mask) { + case BIT(8): + *mc_channel =3D 0; + break; + + case BIT(9): + *mc_channel =3D 1; + break; + + case BIT(10): + *mc_channel =3D 2; + break; + + case BIT(11): + *mc_channel =3D 3; + break; + + case BIT(25): + *mc_channel =3D MC_BROADCAST_CHANNEL; + break; + + default: + pr_err("Unknown interrupt source\n"); + return -EINVAL; + } + + return 0; +} + const struct tegra_mc_soc tegra194_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra194_mc_clients), .clients =3D tegra194_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, + .client_id_mask =3D 0xff, + .intmask =3D MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, + .int_channel_mask =3D 0x2000f00, + .get_int_channel =3D tegra194_mc_get_channel, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 6335a13..8e09fc4 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -93,10 +93,69 @@ static const struct tegra_mc_client tegra234_mc_clients= [] =3D { }, }; =20 +static int tegra234_mc_get_channel(struct tegra_mc *mc, int *mc_channel) +{ + u32 g_intstatus; + + g_intstatus =3D mc_ch_readl(mc, MC_BROADCAST_CHANNEL, + MC_GLOBAL_INTSTATUS); + + switch (g_intstatus & mc->soc->int_channel_mask) { + case BIT(8): + *mc_channel =3D 0; + break; + + case BIT(9): + *mc_channel =3D 1; + break; + + case BIT(10): + *mc_channel =3D 2; + break; + + case BIT(11): + *mc_channel =3D 3; + break; + + case BIT(12): + *mc_channel =3D 4; + break; + + case BIT(13): + *mc_channel =3D 5; + break; + + case BIT(14): + *mc_channel =3D 6; + break; + + case BIT(15): + *mc_channel =3D 7; + break; + + case BIT(25): + *mc_channel =3D MC_BROADCAST_CHANNEL; + break; + + default: + pr_err("Unknown interrupt source\n"); + return -EINVAL; + } + + return 0; +} + const struct tegra_mc_soc tegra234_mc_soc =3D { .num_clients =3D ARRAY_SIZE(tegra234_mc_clients), .clients =3D tegra234_mc_clients, .num_address_bits =3D 40, .num_channels =3D 16, + .intmask =3D MC_INT_DECERR_ROUTE_SANITY | + MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | + MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + .has_addr_hi_reg =3D true, .ops =3D &tegra186_mc_ops, + .int_channel_mask =3D 0x200ff00, + .get_int_channel =3D tegra234_mc_get_channel, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 92f810c..1fe6a62 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -203,6 +203,8 @@ struct tegra_mc_soc { const struct tegra_smmu_soc *smmu; =20 u32 intmask; + u32 int_channel_mask; + bool has_addr_hi_reg; =20 const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; @@ -210,6 +212,8 @@ struct tegra_mc_soc { =20 const struct tegra_mc_icc_ops *icc_ops; const struct tegra_mc_ops *ops; + + int (*get_int_channel)(struct tegra_mc *mc, int *mc_channel); }; =20 struct tegra_mc { --=20 2.7.4