From nobody Tue Jun 23 17:23:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 543E7C433EF for ; Tue, 1 Mar 2022 15:24:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235672AbiCAPZY (ORCPT ); Tue, 1 Mar 2022 10:25:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234830AbiCAPZS (ORCPT ); Tue, 1 Mar 2022 10:25:18 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87B7D8A6E9; Tue, 1 Mar 2022 07:24:34 -0800 (PST) Date: Tue, 01 Mar 2022 15:24:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1646148273; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GVJhdb2BS4mYDpLqZdxym+SAAYZWFezHhoTiZiDZMO8=; b=zgC4GlhMFUt7XMJ0ft04Yo1Ehv+fENoDdxTJOSPOXwBUCVd9q6jb72yc5+QjA0KYKs7uk9 zPFUXo3IT+zvh+F/B1w8Mh59nlK3+GybzIIYm/A2/GMJL/TTS4m4yEB0i8Q6GT/E+/9IXs IUXVXxqLPUjCGLEV1r2izpXORAyViVYKfBMwXb8ylvxqn773/OACHmGYO4aU1Clq+n6YAq hWZ1jYl3yN0ET1RZHgRJQoL1V1GRdYVhYmG2XaOKs8aj/Knqbs/o88aNERlZbYa4/aN6Rp XH/jAmDXisIvdZ96CfPyP1W2/UPZmv61GKaLHTkj1ti5cKFonN2QnKiWKmqrLg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1646148273; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GVJhdb2BS4mYDpLqZdxym+SAAYZWFezHhoTiZiDZMO8=; b=UfQpL3L9XLcUjEl8FVpMYE7watjlZvtdDjIs7usO9C+s67PzCE4zglSr95u8OCiYbmkzee 920CHaQHxXFflgBg== From: "tip-bot2 for Steve Wahl" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-tip-commits@vger.kernel.org Subject: [tip: perf/core] perf/x86/intel/uncore: Make uncore_discovery clean for 64 bit addresses Cc: Steve Wahl , "Peter Zijlstra (Intel)" , Kan Liang , x86@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <20220218175418.421268-1-steve.wahl@hpe.com> References: <20220218175418.421268-1-steve.wahl@hpe.com> MIME-Version: 1.0 Message-ID: <164614827209.16921.9067840905142821813.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the perf/core branch of tip: Commit-ID: 71a412ed4c104bcc239b1a8e06f90b58a4aee0bb Gitweb: https://git.kernel.org/tip/71a412ed4c104bcc239b1a8e06f90b58a= 4aee0bb Author: Steve Wahl AuthorDate: Fri, 18 Feb 2022 11:54:18 -06:00 Committer: Peter Zijlstra CommitterDate: Tue, 01 Mar 2022 16:19:01 +01:00 perf/x86/intel/uncore: Make uncore_discovery clean for 64 bit addresses Support 64-bit BAR size for discovery, and do not truncate return from generic_uncore_mmio_box_ctl() to 32 bits. Signed-off-by: Steve Wahl Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Kan Liang Link: https://lore.kernel.org/r/20220218175418.421268-1-steve.wahl@hpe.com --- arch/x86/events/intel/uncore_discovery.c | 16 +++++++++++----- arch/x86/events/intel/uncore_discovery.h | 2 -- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index 6ddadb4..61185d1 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -210,15 +210,21 @@ static int parse_discovery_table(struct pci_dev *dev,= int die, void __iomem *io_addr; resource_size_t addr; unsigned long size; - u32 val; + u32 val, val2; int i; =20 pci_read_config_dword(dev, bar_offset, &val); =20 - if (val & UNCORE_DISCOVERY_MASK) + if (val & ~PCI_BASE_ADDRESS_MEM_MASK & ~PCI_BASE_ADDRESS_MEM_TYPE_64) return -EINVAL; =20 - addr =3D (resource_size_t)(val & ~UNCORE_DISCOVERY_MASK); + addr =3D (resource_size_t)(val & PCI_BASE_ADDRESS_MEM_MASK); +#ifdef CONFIG_PHYS_ADDR_T_64BIT + if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) =3D=3D PCI_BASE_ADDRESS_MEM_TY= PE_64) { + pci_read_config_dword(dev, bar_offset + 4, &val2); + addr |=3D ((resource_size_t)val2) << 32; + } +#endif size =3D UNCORE_DISCOVERY_GLOBAL_MAP_SIZE; io_addr =3D ioremap(addr, size); if (!io_addr) @@ -444,7 +450,7 @@ static struct intel_uncore_ops generic_uncore_pci_ops = =3D { =20 #define UNCORE_GENERIC_MMIO_SIZE 0x4000 =20 -static unsigned int generic_uncore_mmio_box_ctl(struct intel_uncore_box *b= ox) +static u64 generic_uncore_mmio_box_ctl(struct intel_uncore_box *box) { struct intel_uncore_type *type =3D box->pmu->type; =20 @@ -456,7 +462,7 @@ static unsigned int generic_uncore_mmio_box_ctl(struct = intel_uncore_box *box) =20 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box) { - unsigned int box_ctl =3D generic_uncore_mmio_box_ctl(box); + u64 box_ctl =3D generic_uncore_mmio_box_ctl(box); struct intel_uncore_type *type =3D box->pmu->type; resource_size_t addr; =20 diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index cfaf558..f443935 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -18,8 +18,6 @@ #define UNCORE_DISCOVERY_BIR_BASE 0x10 /* Discovery table BAR step */ #define UNCORE_DISCOVERY_BIR_STEP 0x4 -/* Mask of the discovery table offset */ -#define UNCORE_DISCOVERY_MASK 0xf /* Global discovery table size */ #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20