From nobody Tue Jun 23 17:23:45 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97A74C433EF for ; Tue, 1 Mar 2022 11:12:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234472AbiCALNO (ORCPT ); Tue, 1 Mar 2022 06:13:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232621AbiCALNL (ORCPT ); Tue, 1 Mar 2022 06:13:11 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C14425E5; Tue, 1 Mar 2022 03:12:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646133146; x=1677669146; h=from:to:cc:subject:date:message-id; bh=KqktSACkqjI7XXFCEKdNf7BXOn9rd2j3s7ltokrP7u4=; b=BppDK/yhE2Q1LZL4Khkgc3BDhRP1KZzg3mTXeOEaYh9fAvLpZ3eoyDj1 bnDUqgUdJtjuCUNnchISxXvrICRCI3pOf7wo/lYr6TKFlECG3iiWUf7fp bIiZg17qN39fITOAFrPbd5uTNs5rKUBDGJ6iizuw1xlwIudHbZp5lg0eU U=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 01 Mar 2022 03:12:26 -0800 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 01 Mar 2022 03:12:24 -0800 X-QCInternal: smtphost Received: from c-sbhanu-linux.qualcomm.com ([10.242.50.201]) by ironmsg02-blr.qualcomm.com with ESMTP; 01 Mar 2022 16:42:05 +0530 Received: by c-sbhanu-linux.qualcomm.com (Postfix, from userid 2344807) id DF90E58A9; Tue, 1 Mar 2022 16:42:04 +0530 (IST) From: Shaik Sajida Bhanu To: adrian.hunter@intel.com, ulf.hansson@linaro.org, robh+dt@kernel.org Cc: quic_asutoshd@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sartgarg@quicinc.com, quic_nitirawa@quicinc.com, quic_sayalil@quicinc.com, agross@kernel.org, bjorn.andersson@linaro.org, krzysztof.kozlowski@canonical.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shaik Sajida Bhanu Subject: [PATCH V1] arm64: dts: qcom: sc7280: Add GCC hardware register dt entry Date: Tue, 1 Mar 2022 16:42:03 +0530 Message-Id: <1646133123-22256-1-git-send-email-quic_c_sbhanu@quicinc.com> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add GCC hardware register dt entry for eMMC and SD card. Signed-off-by: Shaik Sajida Bhanu --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index c07765d..2b8461d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -881,6 +881,9 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; =20 + /* Add dt entry for gcc hw reset */ + resets =3D <&gcc GCC_SDCC1_BCR>; + reset-names =3D "core_reset"; sdhc1_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 @@ -2686,6 +2689,9 @@ =20 qcom,dll-config =3D <0x0007642c>; =20 + /* Add dt entry for gcc hw reset */ + resets =3D <&gcc GCC_SDCC2_BCR>; + reset-names =3D "core_reset"; sdhc2_opp_table: opp-table { compatible =3D "operating-points-v2"; =20 --=20 QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member=20 of Code Aurora Forum, hosted by The Linux Foundation