From nobody Tue Jun 23 18:20:16 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E761C4332F for ; Mon, 28 Feb 2022 18:04:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240645AbiB1SDp (ORCPT ); Mon, 28 Feb 2022 13:03:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239680AbiB1RxS (ORCPT ); Mon, 28 Feb 2022 12:53:18 -0500 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E767BAA2EC for ; Mon, 28 Feb 2022 09:40:47 -0800 (PST) Date: Mon, 28 Feb 2022 17:40:42 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1646070043; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J9gn+lq1OxgspfBuH8uvwct2hS/UCwEfO2G29M1/3f8=; b=cxPiqNfpSdXlqHi5fadnPig8ssk3b+7bgpM2d0i2Bup5Qe13CMvtyXzQK1nJkwn9sreZIy ZksYcRVkfo17ShTL+2xmWqgN5DASMTnnNsmTK7RUCKJnYse8lu1AMmEdy9cjo7ZXhzvvWY iYltHyJ4VTjPRcokM7YJLRBMY8NDzQtyLrx9azSGJrasqEPBKt++jLLZM9glsprEzV4nrs PhBikcR5cjJuvxbvzUzOXP1QPPHZMvYoveFGAsCNA5xQzlig4iISQyuN26nrRMtJK6exH1 DeBGtmhgzPPX2PRWwv88efsgbi1GlBtGrNhJtYR1uoYMertwg0aNJ0DcAEpqrA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1646070043; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=J9gn+lq1OxgspfBuH8uvwct2hS/UCwEfO2G29M1/3f8=; b=XTMe+aOEpn/wQJu05p6eNIW2Jgnk2hKHTPDezjHd8iC9/lSyremxQq550tRK7BQso2nveM I25tfiX58kGKd1Aw== From: "irqchip-bot for Marc Zyngier" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQ Cc: Marc Zyngier , tglx@linutronix.de In-Reply-To: <20220224101226.88373-2-maz@kernel.org> References: <20220224101226.88373-2-maz@kernel.org> MIME-Version: 1.0 Message-ID: <164607004262.16921.13704832568538557968.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of ir= qchip: Commit-ID: 9fbc4f3979658ad30f3239d6a3660892976a8206 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-plat= forms/9fbc4f3979658ad30f3239d6a3660892976a8206 Author: Marc Zyngier AuthorDate: Thu, 24 Feb 2022 10:12:22=20 Committer: Marc Zyngier CommitterDate: Mon, 28 Feb 2022 17:32:25=20 irqchip/qcom-pdc: Kill PDC_NO_PARENT_IRQ PDC_NO_PARENT_IRQ is pretty pointless, as all it indicates is that the PDC terminates the interrupt hierarchy. Which is exactly the same as not having a mapping in the GIC space. This is also bad practice to treat the absence of a hwirq as a hwirq itself. Just explicitly use the region mapping pointer, and drop the definition. Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220224101226.88373-2-maz@kernel.org --- drivers/irqchip/qcom-pdc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 173e652..3b214c4 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -30,14 +30,14 @@ #define IRQ_ENABLE_BANK 0x10 #define IRQ_i_CFG 0x110 =20 -#define PDC_NO_PARENT_IRQ ~0UL - struct pdc_pin_region { u32 pin_base; u32 parent_base; u32 cnt; }; =20 +#define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) + static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; static struct pdc_pin_region *pdc_region; @@ -186,19 +186,17 @@ static struct irq_chip qcom_pdc_gic_chip =3D { .irq_set_affinity =3D irq_chip_set_affinity_parent, }; =20 -static irq_hw_number_t get_parent_hwirq(int pin) +static struct pdc_pin_region *get_pin_region(int pin) { int i; - struct pdc_pin_region *region; =20 for (i =3D 0; i < pdc_region_cnt; i++) { - region =3D &pdc_region[i]; - if (pin >=3D region->pin_base && - pin < region->pin_base + region->cnt) - return (region->parent_base + pin - region->pin_base); + if (pin >=3D pdc_region[i].pin_base && + pin < pdc_region[i].pin_base + pdc_region[i].cnt) + return &pdc_region[i]; } =20 - return PDC_NO_PARENT_IRQ; + return NULL; } =20 static int qcom_pdc_translate(struct irq_domain *d, struct irq_fwspec *fws= pec, @@ -221,7 +219,8 @@ static int qcom_pdc_alloc(struct irq_domain *domain, un= signed int virq, { struct irq_fwspec *fwspec =3D data; struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq, parent_hwirq; + struct pdc_pin_region *region; + irq_hw_number_t hwirq; unsigned int type; int ret; =20 @@ -234,8 +233,8 @@ static int qcom_pdc_alloc(struct irq_domain *domain, un= signed int virq, if (ret) return ret; =20 - parent_hwirq =3D get_parent_hwirq(hwirq); - if (parent_hwirq =3D=3D PDC_NO_PARENT_IRQ) + region =3D get_pin_region(hwirq); + if (!region) return irq_domain_disconnect_hierarchy(domain->parent, virq); =20 if (type & IRQ_TYPE_EDGE_BOTH) @@ -247,7 +246,7 @@ static int qcom_pdc_alloc(struct irq_domain *domain, un= signed int virq, parent_fwspec.fwnode =3D domain->parent->fwnode; parent_fwspec.param_count =3D 3; parent_fwspec.param[0] =3D 0; - parent_fwspec.param[1] =3D parent_hwirq; + parent_fwspec.param[1] =3D pin_to_hwirq(region, hwirq); parent_fwspec.param[2] =3D type; =20 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, @@ -265,7 +264,8 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domai= n, unsigned int virq, { struct irq_fwspec *fwspec =3D data; struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq, parent_hwirq; + struct pdc_pin_region *region; + irq_hw_number_t hwirq; unsigned int type; int ret; =20 @@ -281,8 +281,8 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domai= n, unsigned int virq, if (ret) return ret; =20 - parent_hwirq =3D get_parent_hwirq(hwirq); - if (parent_hwirq =3D=3D PDC_NO_PARENT_IRQ) + region =3D get_pin_region(hwirq); + if (!region) return irq_domain_disconnect_hierarchy(domain->parent, virq); =20 if (type & IRQ_TYPE_EDGE_BOTH) @@ -294,7 +294,7 @@ static int qcom_pdc_gpio_alloc(struct irq_domain *domai= n, unsigned int virq, parent_fwspec.fwnode =3D domain->parent->fwnode; parent_fwspec.param_count =3D 3; parent_fwspec.param[0] =3D 0; - parent_fwspec.param[1] =3D parent_hwirq; + parent_fwspec.param[1] =3D pin_to_hwirq(region, hwirq); parent_fwspec.param[2] =3D type; =20 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,