From nobody Tue Jun 23 21:32:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF91C433EF for ; Fri, 25 Feb 2022 15:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242532AbiBYP7F (ORCPT ); Fri, 25 Feb 2022 10:59:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242513AbiBYP67 (ORCPT ); Fri, 25 Feb 2022 10:58:59 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59B95186432; Fri, 25 Feb 2022 07:58:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645804707; x=1677340707; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=7UCNu88R5r7rsyWiBT1P3baB0nFrj2ADgGHSvTpTj0w=; b=L+VMfW5QofFIdOSFlEDc1w8Fuky6WZUb3GBSKWmA0ElPY2AWBofndRvZ g4zdWBkMMabG5N7qEK3CoYs1YEvd+mbxK0ZOR8YbWvLuS+DRdEmYwpgkw xt1+6Hlb0wS7VfyT4MHE2QdXnC0q5cKWrWzIDQcFOyeWcaKgNtFVPxf6b U=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 25 Feb 2022 07:58:27 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 25 Feb 2022 07:58:26 -0800 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg01-blr.qualcomm.com with ESMTP; 25 Feb 2022 21:28:15 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id EB57153E9; Fri, 25 Feb 2022 21:28:14 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v2 1/2] arm64/dts/qcom/sc7280: remove assigned-clock-rate property for mdp clk Date: Fri, 25 Feb 2022 21:27:49 +0530 Message-Id: <1645804670-21898-2-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645804670-21898-1-git-send-email-quic_vpolimer@quicinc.com> References: <1645804670-21898-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Kernel clock driver assumes that initial rate is the max rate for that clock and was not allowing it to scale beyond the assigned clock value. drop the assigned clock rate property and set it during resume sequence with max value in the opp table. Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Signed-off-by: Vinod Polimera --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index baf1653..408cf6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2856,9 +2856,6 @@ "ahb", "core"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>; - assigned-clock-rates =3D <300000000>; - interrupts =3D ; interrupt-controller; #interrupt-cells =3D <1>; @@ -2892,11 +2889,9 @@ "lut", "core", "vsync"; - assigned-clocks =3D <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>, <&dispcc DISP_CC_MDSS_AHB_CLK>; - assigned-clock-rates =3D <300000000>, - <19200000>, + assigned-clock-rates =3D <19200000>, <19200000>; operating-points-v2 =3D <&mdp_opp_table>; power-domains =3D <&rpmhpd SC7280_CX>; --=20 2.7.4 From nobody Tue Jun 23 21:32:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCCD6C4332F for ; Fri, 25 Feb 2022 15:58:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242531AbiBYP7C (ORCPT ); Fri, 25 Feb 2022 10:59:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242508AbiBYP66 (ORCPT ); Fri, 25 Feb 2022 10:58:58 -0500 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4218186440; Fri, 25 Feb 2022 07:58:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645804706; x=1677340706; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=VDbp786rZJt995Eu/NdhIPojDHjLi2BsoWetqwF1jHE=; b=OZRErQREuQ+WKjBCaKwnncBP74vE7k4y3gbHKQOLf5NBiJtMt3NG6/6p I88S3psm6id8HOciriHEsybydx3ckEP4rnLh9OKCnf6P0P4Kn2K9n5Sy/ OtKfl5GVWEqsEj7rY4cWeYHjkbMtVNQ7j7KnV1dZ2+ftKAKDryKM1Oo+9 8=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 25 Feb 2022 07:58:25 -0800 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 25 Feb 2022 07:58:24 -0800 X-QCInternal: smtphost Received: from vpolimer-linux.qualcomm.com ([10.204.67.235]) by ironmsg01-blr.qualcomm.com with ESMTP; 25 Feb 2022 21:28:17 +0530 Received: by vpolimer-linux.qualcomm.com (Postfix, from userid 463814) id CF14453E9; Fri, 25 Feb 2022 21:28:16 +0530 (IST) From: Vinod Polimera To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org Cc: Vinod Polimera , linux-kernel@vger.kernel.org, robdclark@gmail.com, dianders@chromium.org, swboyd@chromium.org, quic_kalyant@quicinc.com Subject: [PATCH v2 2/2] drm/msm/disp/dpu1: set mdp clk to the maximum frequency in opp table Date: Fri, 25 Feb 2022 21:27:50 +0530 Message-Id: <1645804670-21898-3-git-send-email-quic_vpolimer@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1645804670-21898-1-git-send-email-quic_vpolimer@quicinc.com> References: <1645804670-21898-1-git-send-email-quic_vpolimer@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" use max clock during resume sequence from the opp table. The clock will be scaled down when framework sends an update. Fixes: 62fbdce91("arm64: dts: qcom: sc7280: add display dt nodes") Signed-off-by: Vinod Polimera --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d550f90..3288f52 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1319,6 +1319,7 @@ static int __maybe_unused dpu_runtime_resume(struct d= evice *dev) struct drm_device *ddev; struct dss_module_power *mp =3D &dpu_kms->mp; int i; + unsigned long max_freq =3D ULONG_MAX; =20 ddev =3D dpu_kms->dev; =20 @@ -1333,6 +1334,8 @@ static int __maybe_unused dpu_runtime_resume(struct d= evice *dev) return rc; } =20 + dev_pm_opp_find_freq_floor(dev, &max_freq); + dev_pm_opp_set_rate(dev, max_freq); dpu_vbif_init_memtypes(dpu_kms); =20 drm_for_each_encoder(encoder, ddev) --=20 2.7.4