From nobody Sun Sep 22 07:34:26 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56E70C433F5 for ; Fri, 25 Feb 2022 09:54:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239282AbiBYJyp (ORCPT ); Fri, 25 Feb 2022 04:54:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239275AbiBYJyl (ORCPT ); Fri, 25 Feb 2022 04:54:41 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C677254544 for ; Fri, 25 Feb 2022 01:54:09 -0800 (PST) X-UUID: b6ddab556d1f422484d9e515e4cee17e-20220225 X-UUID: b6ddab556d1f422484d9e515e4cee17e-20220225 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2068206144; Fri, 25 Feb 2022 17:54:04 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 25 Feb 2022 17:54:03 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Feb 2022 17:54:02 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Feb 2022 17:54:01 +0800 From: To: , , , , CC: , , , , , , , , Xinlei Lee Subject: [PATCH v1,2/3] drm/mediatek: Add TOPCKGEN select mux control dpi_clk Date: Fri, 25 Feb 2022 17:53:52 +0800 Message-ID: <1645782833-27875-3-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1645782833-27875-1-git-send-email-xinlei.lee@mediatek.com> References: <1645782833-27875-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Dpi_clk is controlled by the mux selected by TOPCKGEN and APMIXEDSYS can support small resolution. Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dpi.c | 38 ++++++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 4554e2de1430..bad686817e29 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -63,6 +63,14 @@ enum mtk_dpi_out_color_format { MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL }; =20 +enum TVDPLL_CLK { + TVDPLL_PLL =3D 0, + TVDPLL_D2 =3D 2, + TVDPLL_D4 =3D 4, + TVDPLL_D8 =3D 8, + TVDPLL_D16 =3D 16, +}; + struct mtk_dpi { struct drm_encoder encoder; struct drm_bridge bridge; @@ -73,6 +81,7 @@ struct mtk_dpi { struct clk *engine_clk; struct clk *pixel_clk; struct clk *tvd_clk; + struct clk *pclk_src[5]; int irq; struct drm_display_mode mode; const struct mtk_dpi_conf *conf; @@ -459,6 +468,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct videomode vm =3D { 0 }; unsigned long pll_rate; unsigned int factor; + struct clk *clksrc =3D NULL; =20 /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ factor =3D dpi->conf->cal_factor(mode->clock); @@ -473,11 +483,26 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, =20 vm.pixelclock =3D pll_rate / factor; if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) - clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else - clk_set_rate(dpi->pixel_clk, vm.pixelclock); + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) { + if (factor =3D=3D 8) + clksrc =3D dpi->pclk_src[2]; + else if (factor =3D=3D 4) + clksrc =3D dpi->pclk_src[1]; + else + clksrc =3D dpi->pclk_src[1]; + } + else { + if (factor =3D=3D 8) + clksrc =3D dpi->pclk_src[3]; + else if (factor =3D=3D 4) + clksrc =3D dpi->pclk_src[2]; + else + clksrc =3D dpi->pclk_src[2]; + } =20 + clk_prepare_enable(dpi->pixel_clk); + clk_set_parent(dpi->pixel_clk, clksrc); + clk_disable_unprepare(dpi->pixel_clk); =20 vm.pixelclock =3D clk_get_rate(dpi->pixel_clk); =20 @@ -893,6 +918,11 @@ static int mtk_dpi_probe(struct platform_device *pdev) return ret; } =20 + dpi->pclk_src[1] =3D devm_clk_get_optional(dev, "tvdpll_d2"); + dpi->pclk_src[2] =3D devm_clk_get_optional(dev, "tvdpll_d4"); + dpi->pclk_src[3] =3D devm_clk_get_optional(dev, "tvdpll_d8"); + dpi->pclk_src[4] =3D devm_clk_get_optional(dev, "tvdpll_d16"); + dpi->irq =3D platform_get_irq(pdev, 0); if (dpi->irq <=3D 0) return -EINVAL; --=20 2.18.0