From nobody Sun Sep 22 07:25:04 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A669EC433F5 for ; Fri, 18 Feb 2022 10:08:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233862AbiBRKI0 (ORCPT ); Fri, 18 Feb 2022 05:08:26 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:54796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231401AbiBRKIY (ORCPT ); Fri, 18 Feb 2022 05:08:24 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F29301D329 for ; Fri, 18 Feb 2022 02:08:07 -0800 (PST) X-UUID: 4b27a5d911474e6fa7987c69523819f7-20220218 X-UUID: 4b27a5d911474e6fa7987c69523819f7-20220218 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 971303730; Fri, 18 Feb 2022 18:08:03 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 18:08:02 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 18 Feb 2022 18:08:01 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 18 Feb 2022 18:07:58 +0800 From: To: , , , , CC: , , , , , , , , Xinlei Lee Subject: [PATCH v2,1/3] dt-bindings: display: mediatek: dsi: Convert dsi_dtbinding to .yaml Date: Fri, 18 Feb 2022 18:07:47 +0800 Message-ID: <1645178869-18048-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1645178869-18048-1-git-send-email-xinlei.lee@mediatek.com> References: <1645178869-18048-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xinlei Lee Convert mediatek,dsi.txt to mediatek,dsi.yaml format Signed-off-by: Xinlei Lee --- .../display/mediatek/mediatek,dsi.txt | 62 -------------- .../display/mediatek/mediatek,dsi.yaml | 85 +++++++++++++++++++ 2 files changed, 85 insertions(+), 62 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dsi.txt create mode 100644 Documentation/devicetree/bindings/display/mediatek/medi= atek,dsi.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt deleted file mode 100644 index 36b01458f45c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ /dev/null @@ -1,62 +0,0 @@ -Mediatek DSI Device -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -The Mediatek DSI function block is a sink of the display subsystem and can -drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual- -channel output. - -Required properties: -- compatible: "mediatek,-dsi" -- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183. -- reg: Physical base address and length of the controller's registers -- interrupts: The interrupt signal from the function block. -- clocks: device clocks - See Documentation/devicetree/bindings/clock/clock-bindings.txt for detai= ls. -- clock-names: must contain "engine", "digital", and "hs" -- phys: phandle link to the MIPI D-PHY controller. -- phy-names: must contain "dphy" -- port: Output port node with endpoint definitions as described in - Documentation/devicetree/bindings/graph.txt. This port should be connect= ed - to the input port of an attached DSI panel or DSI-to-eDP encoder chip. - -Optional properties: -- resets: list of phandle + reset specifier pair, as described in [1]. - -[1] Documentation/devicetree/bindings/reset/reset.txt - -MIPI TX Configuration Module -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D - -See phy/mediatek,dsi-phy.yaml - -Example: - -mipi_tx0: mipi-dphy@10215000 { - compatible =3D "mediatek,mt8173-mipi-tx"; - reg =3D <0 0x10215000 0 0x1000>; - clocks =3D <&clk26m>; - clock-output-names =3D "mipi_tx0_pll"; - #clock-cells =3D <0>; - #phy-cells =3D <0>; - drive-strength-microamp =3D <4600>; - nvmem-cells=3D <&mipi_tx_calibration>; - nvmem-cell-names =3D "calibration-data"; -}; - -dsi0: dsi@1401b000 { - compatible =3D "mediatek,mt8173-dsi"; - reg =3D <0 0x1401b000 0 0x1000>; - interrupts =3D ; - clocks =3D <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>, - <&mipi_tx0>; - clock-names =3D "engine", "digital", "hs"; - resets =3D <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; - phys =3D <&mipi_tx0>; - phy-names =3D "dphy"; - - port { - dsi0_out: endpoint { - remote-endpoint =3D <&panel_in>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.ya= ml new file mode 100644 index 000000000000..552a013786fe --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: mediatek DSI Controller Device Tree Bindings + +maintainers: + - CK Hu + - Jitao Shi + - Xinlei Lee + +properties: + compatible: + enum: + - mediatek,mt2701-dsi + - mediatek,mt8173-dsi + - mediatek,mt8183-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Engine Clock + - description: Digital Clock + - description: Hs Clock + + clock-names: + items: + - const: engine + - const: digital + - const: hs + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + items: + - const: dphy + +required: + - compatible + - reg + - interrupts + - power-domains + - clocks + - clock-names + - phys + - phy-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + dsi0: dsi@14014000 { + compatible =3D "mediatek,mt8183-dsi"; + reg =3D <0x14014000 0x1000>; + interrupts =3D ; + power-domains =3D <&spm MT8183_POWER_DOMAIN_DISP>; + clocks =3D <&mmsys CLK_MM_DSI0_MM>, + <&mmsys CLK_MM_DSI0_IF>, + <&mipi_tx0>; + clock-names =3D "engine", "digital", "hs"; + resets =3D <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; + phys =3D <&mipi_tx0>; + phy-names =3D "dphy"; + }; --=20 2.18.0