From nobody Sun Sep 22 09:39:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3660EC433EF for ; Fri, 11 Feb 2022 14:30:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350841AbiBKOap (ORCPT ); Fri, 11 Feb 2022 09:30:45 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34408 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245641AbiBKOam (ORCPT ); Fri, 11 Feb 2022 09:30:42 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B4B5CF for ; Fri, 11 Feb 2022 06:30:40 -0800 (PST) X-UUID: 7923fb5ef84a4764b1e0340c622ddb51-20220211 X-UUID: 7923fb5ef84a4764b1e0340c622ddb51-20220211 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1223725421; Fri, 11 Feb 2022 22:30:38 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Feb 2022 22:30:37 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Feb 2022 22:30:35 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Feb 2022 22:30:29 +0800 From: To: , , , , CC: , , , , , , Jitao Shi , Xinlei Lee Subject: [1/3] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 Date: Fri, 11 Feb 2022 22:30:15 +0800 Message-ID: <1644589818-13066-2-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> References: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitao Shi In order to cooperate with patch 3/3 modification,it is necessary to adjust=20 the position where mipi pulls up the signal. Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 5d90d2eb..6d7b66d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_phy_timconfig(dsi); =20 - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); mtk_dsi_ps_control_vact(dsi); mtk_dsi_set_vm_cmd(dsi); mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); =20 + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); mtk_dsi_clk_ulp_mode_leave(dsi); mtk_dsi_lane0_ulp_mode_leave(dsi); mtk_dsi_clk_hs_mode(dsi, 0); --=20 2.6.4 From nobody Sun Sep 22 09:39:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B94CEC433F5 for ; Fri, 11 Feb 2022 14:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350844AbiBKOax (ORCPT ); Fri, 11 Feb 2022 09:30:53 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233819AbiBKOaw (ORCPT ); Fri, 11 Feb 2022 09:30:52 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79C6AB3F for ; Fri, 11 Feb 2022 06:30:51 -0800 (PST) X-UUID: 58c4f3ad734e4f55be69433b3f57211a-20220211 X-UUID: 58c4f3ad734e4f55be69433b3f57211a-20220211 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 70064850; Fri, 11 Feb 2022 22:30:47 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 11 Feb 2022 22:30:46 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Feb 2022 22:30:44 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Feb 2022 22:30:38 +0800 From: To: , , , , CC: , , , , , , Jitao Shi , Xinlei Lee Subject: [2/3] drm/mediatek: Separate poweron/poweroff from enable/disable and define new funcs Date: Fri, 11 Feb 2022 22:30:16 +0800 Message-ID: <1644589818-13066-3-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> References: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitao Shi In order to match the changes of DSI RX devices (for example, anx7625),=20 the poweron/poweroff of dsi is extracted from enable/disable and=20 defined as new funcs (pre_enable/post_disable). Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dsi.c | 45 ++++++++++++++++++++++------------= ---- 1 file changed, 26 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index 6d7b66d..e47c338 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -679,16 +679,6 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) if (--dsi->refcount !=3D 0) return; =20 - /* - * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since - * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), - * which needs irq for vblank, and mtk_dsi_stop() will disable irq. - * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), - * after dsi is fully set. - */ - mtk_dsi_stop(dsi); - - mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); mtk_dsi_reset_engine(dsi); mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); @@ -703,17 +693,9 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) =20 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) { - int ret; - if (dsi->enabled) return; =20 - ret =3D mtk_dsi_poweron(dsi); - if (ret < 0) { - DRM_ERROR("failed to power on dsi\n"); - return; - } - mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); =20 @@ -727,7 +709,16 @@ static void mtk_output_dsi_disable(struct mtk_dsi *dsi) if (!dsi->enabled) return; =20 - mtk_dsi_poweroff(dsi); + /* + * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since + * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(), + * which needs irq for vblank, and mtk_dsi_stop() will disable irq. + * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(), + * after dsi is fully set. + */ + mtk_dsi_stop(dsi); + + mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500); =20 dsi->enabled =3D false; } @@ -765,10 +756,26 @@ static void mtk_dsi_bridge_enable(struct drm_bridge *= bridge) mtk_output_dsi_enable(dsi); } =20 +static void mtk_dsi_bridge_pre_enable(struct drm_bridge *bridge) +{ + struct mtk_dsi *dsi =3D bridge_to_dsi(bridge); + + mtk_dsi_poweron(dsi); +} + +static void mtk_dsi_bridge_post_disable(struct drm_bridge *bridge) +{ + struct mtk_dsi *dsi =3D bridge_to_dsi(bridge); + + mtk_dsi_poweroff(dsi); +} + static const struct drm_bridge_funcs mtk_dsi_bridge_funcs =3D { .attach =3D mtk_dsi_bridge_attach, .disable =3D mtk_dsi_bridge_disable, .enable =3D mtk_dsi_bridge_enable, + .pre_enable =3D mtk_dsi_bridge_pre_enable, + .post_disable =3D mtk_dsi_bridge_post_disable, .mode_set =3D mtk_dsi_bridge_mode_set, }; =20 --=20 2.6.4 From nobody Sun Sep 22 09:39:54 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A84E6C433EF for ; Fri, 11 Feb 2022 14:31:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350826AbiBKObC (ORCPT ); Fri, 11 Feb 2022 09:31:02 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:34608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350848AbiBKObB (ORCPT ); Fri, 11 Feb 2022 09:31:01 -0500 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64827BA9 for ; Fri, 11 Feb 2022 06:31:00 -0800 (PST) X-UUID: 16d9a88f67fd4d2a812a9eae3fb13f32-20220211 X-UUID: 16d9a88f67fd4d2a812a9eae3fb13f32-20220211 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 764078913; Fri, 11 Feb 2022 22:30:55 +0800 Received: from MTKMBS34N1.mediatek.inc (172.27.4.172) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 11 Feb 2022 22:30:53 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS34N1.mediatek.inc (172.27.4.172) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Feb 2022 22:30:52 +0800 Received: from mszsdaap41.gcn.mediatek.inc (10.16.6.141) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 11 Feb 2022 22:30:47 +0800 From: To: , , , , CC: , , , , , , Jitao Shi , Xinlei Lee Subject: [3/3] drm/mediatek: keep dsi as LP00 before dcs cmds transfer Date: Fri, 11 Feb 2022 22:30:17 +0800 Message-ID: <1644589818-13066-4-git-send-email-xinlei.lee@mediatek.com> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> References: <1644589818-13066-1-git-send-email-xinlei.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jitao Shi To comply with the panel sequence, hold the mipi signal to LP00 before the = dcs cmds transmission,=20 and pull the mipi signal high from LP00 to LP11 until the start of the dcs = cmds transmission. If dsi is not in cmd mode, then dsi will pull the mipi signal high in the m= tk_output_dsi_enable function. Signed-off-by: Jitao Shi Signed-off-by: Xinlei Lee --- drivers/gpu/drm/mediatek/mtk_dsi.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/= mtk_dsi.c index e47c338..17a5270 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -203,6 +203,7 @@ struct mtk_dsi { struct mtk_phy_timing phy_timing; int refcount; bool enabled; + bool lanes_ready; u32 irq_data; wait_queue_head_t irq_wait_queue; const struct mtk_dsi_driver_data *driver_data; @@ -654,13 +655,6 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) mtk_dsi_config_vdo_timing(dsi); mtk_dsi_set_interrupt_enable(dsi); =20 - mtk_dsi_rxtx_control(dsi); - usleep_range(30, 100); - mtk_dsi_reset_dphy(dsi); - mtk_dsi_clk_ulp_mode_leave(dsi); - mtk_dsi_lane0_ulp_mode_leave(dsi); - mtk_dsi_clk_hs_mode(dsi, 0); - return 0; err_disable_engine_clk: clk_disable_unprepare(dsi->engine_clk); @@ -682,6 +676,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) mtk_dsi_reset_engine(dsi); mtk_dsi_lane0_ulp_mode_enter(dsi); mtk_dsi_clk_ulp_mode_enter(dsi); + /* set the lane number as 0 */ + writel(0, dsi->regs + DSI_TXRX_CTRL); =20 mtk_dsi_disable(dsi); =20 @@ -689,6 +685,8 @@ static void mtk_dsi_poweroff(struct mtk_dsi *dsi) clk_disable_unprepare(dsi->digital_clk); =20 phy_power_off(dsi->phy); + + dsi->lanes_ready =3D false; } =20 static void mtk_output_dsi_enable(struct mtk_dsi *dsi) @@ -696,6 +694,16 @@ static void mtk_output_dsi_enable(struct mtk_dsi *dsi) if (dsi->enabled) return; =20 + if (!dsi->lanes_ready) { + dsi->lanes_ready =3D true; + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); + mtk_dsi_clk_ulp_mode_leave(dsi); + mtk_dsi_lane0_ulp_mode_leave(dsi); + mtk_dsi_clk_hs_mode(dsi, 0); + } + mtk_dsi_set_mode(dsi); mtk_dsi_clk_hs_mode(dsi, 1); =20 @@ -907,6 +915,16 @@ static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_h= ost *host, if (MTK_DSI_HOST_IS_READ(msg->type)) irq_flag |=3D LPRX_RD_RDY_INT_FLAG; =20 + if (!dsi->lanes_ready) { + dsi->lanes_ready =3D true; + mtk_dsi_rxtx_control(dsi); + usleep_range(30, 100); + mtk_dsi_reset_dphy(dsi); + mtk_dsi_clk_ulp_mode_leave(dsi); + mtk_dsi_lane0_ulp_mode_leave(dsi); + mtk_dsi_clk_hs_mode(dsi, 0); + msleep(20); + } if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0) return -ETIME; =20 --=20 2.6.4